uart_test.ide_des

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· IDE_DES 代码 · 共 19 行

KEY IDE_DES_TOOL "Designer"
KEY IDE_DES_FAMILY "ProASIC3"
KEY IDE_DES_DIE "IQ2X1M0"
KEY IDE_DES_PACKAGE "vq100"
KEY IDE_DES_TOP_CELL_NAME "uart_test"
KEY IDE_DES_KEEP_PHY_CONSTR "TRUE"
KEY IDE_DES_KEEP_TIME_CONSTR "TRUE"
KEY IDE_DES_LAYOUT_DONE "TRUE"
KEY IDE_DES_BA_EXPORTED "FALSE"
KEY IDE_DES_ERROR_FOUND "FALSE"
KEY IDE_DES_ADB_PATH "E:\programer_new\UART\project\designer\impl1\uart_test.adb"
LIST SOURCE_FILES
VALUE "E:\programer_new\UART\project\synthesis\uart_test.edn;edn"
VALUE "E:\programer_new\UART\project\synthesis\uart_test_sdc.sdc;sdc"
ENDLIST
LIST OPTIONAL_FILES
VALUE "E:\programer_new\UART\project\synthesis\uart_test_sdc.sdc;Used"
ENDLIST