📄 uart_test.srr
字号:
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.550 0.550 -
count[0] Net - - 1.140 - 7
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B B In - 1.690 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B Y Out 0.469 2.158 -
N_7 Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 A In - 2.398 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 Y Out 0.365 2.763 -
I_9_0 Net - - 0.884 - 4
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A C In - 3.647 -
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A Y Out 0.479 4.126 -
bit_collect34 Net - - 0.955 - 5
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 B In - 5.081 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 Y Out 0.469 5.550 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B A In - 5.838 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B Y Out 0.384 6.222 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_18 XOR2 B In - 6.510 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_18 XOR2 Y Out 0.700 7.210 -
count_bit_4[2] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 B In - 7.498 -
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 Y Out 0.674 8.172 -
RI18 Net - - 0.602 - 3
uartrec.count_bit_4.resyn_0.uartrec.un1_RXD[0] MX2C B In - 8.774 -
uartrec.count_bit_4.resyn_0.uartrec.un1_RXD[0] MX2C Y Out 0.437 9.211 -
un1_RXD[0] Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A A In - 9.452 -
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A Y Out 0.432 9.884 -
RI_5 Net - - 0.240 - 1
uartrec.RI DFN1E0 D In - 10.124 -
=====================================================================================================================
Total path delay (propagation time + setup) of 10.526 is 5.360(50.9%) logic and 5.166(49.1%) route.
Path information for path number 4:
Requested Period: 10.000
- Setup time: 0.402
= Required time: 9.598
- Propagation time: 10.108
= Slack (non-critical) : -0.511
Number of logic level(s): 10
Starting point: uartrec.count[0] / Q
Ending point: uartrec.RI / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.550 0.550 -
count[0] Net - - 1.140 - 7
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_12 AND3 A In - 1.690 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_12 AND3 Y Out 0.346 2.036 -
N_4 Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_13 XOR2 A In - 2.277 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_13 XOR2 Y Out 0.305 2.582 -
I_13_0 Net - - 0.602 - 3
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A A In - 3.184 -
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A Y Out 0.479 3.663 -
bit_collect34 Net - - 0.955 - 5
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 B In - 4.618 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 Y Out 0.469 5.087 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B A In - 5.375 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B Y Out 0.384 5.759 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_21 NOR2B A In - 6.047 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_21 NOR2B Y Out 0.384 6.431 -
DWACT_ADD_CI_0_g_array_12[0] Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_17 XOR2 B In - 6.671 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_17 XOR2 Y Out 0.700 7.371 -
RI18lto3 Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 C In - 7.659 -
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 Y Out 0.497 8.156 -
RI18 Net - - 0.602 - 3
uartrec.count_bit_4.resyn_0.uartrec.un1_RXD[0] MX2C B In - 8.759 -
uartrec.count_bit_4.resyn_0.uartrec.un1_RXD[0] MX2C Y Out 0.437 9.196 -
un1_RXD[0] Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A A In - 9.436 -
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A Y Out 0.432 9.868 -
RI_5 Net - - 0.240 - 1
uartrec.RI DFN1E0 D In - 10.108 -
=====================================================================================================================
Total path delay (propagation time + setup) of 10.511 is 5.386(51.2%) logic and 5.124(48.8%) route.
Path information for path number 5:
Requested Period: 10.000
- Setup time: 0.402
= Required time: 9.598
- Propagation time: 10.091
= Slack (non-critical) : -0.494
Number of logic level(s): 9
Starting point: uartrec.count[0] / Q
Ending point: uartrec.RI / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.550 0.550 -
count[0] Net - - 1.140 - 7
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B B In - 1.690 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B Y Out 0.469 2.158 -
N_7 Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 A In - 2.398 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 Y Out 0.365 2.763 -
I_9_0 Net - - 0.884 - 4
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A C In - 3.647 -
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A Y Out 0.479 4.126 -
bit_collect34 Net - - 0.955 - 5
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 B In - 5.081 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 Y Out 0.469 5.550 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B A In - 5.838 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B Y Out 0.384 6.222 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_18 XOR2 B In - 6.510 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_18 XOR2 Y Out 0.700 7.210 -
count_bit_4[2] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 B In - 7.498 -
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 Y Out 0.674 8.172 -
RI18 Net - - 0.602 - 3
uartrec.count_bit_4.resyn_0.uartrec.RI_2_sqmuxa NOR3A C In - 8.774 -
uartrec.count_bit_4.resyn_0.uartrec.RI_2_sqmuxa NOR3A Y Out 0.479 9.253 -
RI_2_sqmuxa Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A S In - 9.493 -
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A Y Out 0.358 9.851 -
RI_5 Net - - 0.240 - 1
uartrec.RI DFN1E0 D In - 10.091 -
=====================================================================================================================
Total path delay (propagation time + setup) of 10.494 is 5.328(50.8%) logic and 5.166(49.2%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell uart_test.verilog
Core Cell usage:
cell count area count*area
AND2 8 1.0 8.0
AND3 41 1.0 41.0
AO1 1 1.0 1.0
AOI1B 1 1.0 1.0
BUFF 1 1.0 1.0
GND 3 0.0 0.0
INV 1 1.0 1.0
MAJ3 1 1.0 1.0
MX2 6 1.0 6.0
MX2A 1 1.0 1.0
MX2C 9 1.0 9.0
NOR2 8 1.0 8.0
NOR2A 25 1.0 25.0
NOR2B 26 1.0 26.0
NOR3 1 1.0 1.0
NOR3A 8 1.0 8.0
NOR3B 5 1.0 5.0
NOR3C 8 1.0 8.0
OA1 5 1.0 5.0
OA1C 1 1.0 1.0
OAI1 2 1.0 2.0
OR2 3 1.0 3.0
OR2A 2 1.0 2.0
OR2B 5 1.0 5.0
OR3A 1 1.0 1.0
VCC 3 0.0 0.0
XA1 3 1.0 3.0
XOR2 44 1.0 44.0
DFN1 48 1.0 48.0
DFN1E0 13 1.0 13.0
DFN1E1 20 1.0 20.0
----- ----------
TOTAL 304 298.0
IO Cell usage:
cell count
CLKBUF 1
INBUF 1
OUTBUF 1
-----
TOTAL 3
Core Cells : 298 of 768 (39%)
IO Cells : 3
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Jul 05 08:23:29 2008
###########################################################]
Total runtime: 00h:00m:03s realtime
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