📄 uart_test.srr
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=========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.428
= Required time: 9.572
- Propagation time: 0.839
= Slack (non-critical) : 8.733
Number of logic level(s): 0
Starting point: WR_R1 / Q
Ending point: WR_R2 / D
The start point is clocked by send|clkout_inferred_clock [rising] on pin CLK
The end point is clocked by send|clkout_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
WR_R1 DFN1 Q Out 0.550 0.550 -
WR_R1 Net - - 0.288 - 2
WR_R2 DFN1 D In - 0.839 -
=============================================================================
Total path delay (propagation time + setup) of 1.267 is 0.979(77.2%) logic and 0.288(22.8%) route.
====================================
Detailed Report for Clock: uart_test|clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------
uartrec.count[0] uart_test|clock DFN1E0 Q count[0] 0.550 -0.974
uartrec.count[1] uart_test|clock DFN1E0 Q count[1] 0.550 -0.352
uartrec.count[2] uart_test|clock DFN1E0 Q count[2] 0.550 0.208
uartrec.cnt[3] uart_test|clock DFN1 Q cnt[3] 0.550 0.333
uartrec.cnt[13] uart_test|clock DFN1 Q cnt[13] 0.550 0.560
uartrec.cnt[0] uart_test|clock DFN1 Q cnt[0] 0.550 0.581
uartrec.cnt[10] uart_test|clock DFN1 Q cnt[10] 0.550 0.664
uartrec.count[3] uart_test|clock DFN1E0 Q count[3] 0.550 0.686
uartrec.cnt[8] uart_test|clock DFN1 Q cnt[8] 0.550 1.186
uartrec.cnt[9] uart_test|clock DFN1 Q cnt[9] 0.550 1.194
===========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
uartrec.StartF uart_test|clock DFN1E0 D StartF_6 9.572 -0.328
uartrec.count_bit[3] uart_test|clock DFN1 D count_bit_1[3] 9.598 0.060
uartrec.UartBuff[8] uart_test|clock DFN1E1 E UartBuff_15_e 9.546 0.333
uartrec.UartBuff[1] uart_test|clock DFN1E1 E N_87_i 9.546 0.429
uartrec.UartBuff[2] uart_test|clock DFN1E1 E N_89_i 9.546 0.429
uartrec.UartBuff[3] uart_test|clock DFN1E1 E N_91_i 9.546 0.429
uartrec.UartBuff[4] uart_test|clock DFN1E1 E N_93_i 9.546 0.429
uartrec.UartBuff[5] uart_test|clock DFN1E1 E N_95_i 9.546 0.429
uartrec.UartBuff[6] uart_test|clock DFN1E1 E N_97_i 9.546 0.429
uartrec.UartBuff[7] uart_test|clock DFN1E1 E N_99_i 9.546 0.429
======================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.402
= Required time: 9.598
- Propagation time: 10.572
= Slack (critical) : -0.974
Number of logic level(s): 10
Starting point: uartrec.count[0] / Q
Ending point: uartrec.RI / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.550 0.550 -
count[0] Net - - 1.140 - 7
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B B In - 1.690 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B Y Out 0.469 2.158 -
N_7 Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 A In - 2.398 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 Y Out 0.365 2.763 -
I_9_0 Net - - 0.884 - 4
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A C In - 3.647 -
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A Y Out 0.479 4.126 -
bit_collect34 Net - - 0.955 - 5
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 B In - 5.081 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 Y Out 0.469 5.550 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B A In - 5.838 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B Y Out 0.384 6.222 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_21 NOR2B A In - 6.510 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_21 NOR2B Y Out 0.384 6.895 -
DWACT_ADD_CI_0_g_array_12[0] Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_17 XOR2 B In - 7.135 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_17 XOR2 Y Out 0.700 7.834 -
RI18lto3 Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 C In - 8.123 -
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 Y Out 0.497 8.620 -
RI18 Net - - 0.602 - 3
uartrec.count_bit_4.resyn_0.uartrec.un1_RXD[0] MX2C B In - 9.222 -
uartrec.count_bit_4.resyn_0.uartrec.un1_RXD[0] MX2C Y Out 0.437 9.659 -
un1_RXD[0] Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A A In - 9.899 -
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A Y Out 0.432 10.332 -
RI_5 Net - - 0.240 - 1
uartrec.RI DFN1E0 D In - 10.572 -
=====================================================================================================================
Total path delay (propagation time + setup) of 10.974 is 5.568(50.7%) logic and 5.406(49.3%) route.
Path information for path number 2:
Requested Period: 10.000
- Setup time: 0.402
= Required time: 9.598
- Propagation time: 10.539
= Slack (non-critical) : -0.941
Number of logic level(s): 10
Starting point: uartrec.count[0] / Q
Ending point: uartrec.RI / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.550 0.550 -
count[0] Net - - 1.140 - 7
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B B In - 1.690 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_8 NOR2B Y Out 0.469 2.158 -
N_7 Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 A In - 2.398 -
uartrec.count_bit_4.resyn_0.uartrec.un9_count_1.I_9 XOR2 Y Out 0.365 2.763 -
I_9_0 Net - - 0.884 - 4
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A C In - 3.647 -
uartrec.count_bit_4.resyn_0.uartrec.bit_collect34 NOR3A Y Out 0.479 4.126 -
bit_collect34 Net - - 0.955 - 5
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 B In - 5.081 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_1 AND2 Y Out 0.469 5.550 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B A In - 5.838 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_19 NOR2B Y Out 0.384 6.222 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_21 NOR2B A In - 6.510 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_21 NOR2B Y Out 0.384 6.895 -
DWACT_ADD_CI_0_g_array_12[0] Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_17 XOR2 B In - 7.135 -
uartrec.count_bit_4.resyn_0.uartrec.count_bit_4.I_17 XOR2 Y Out 0.700 7.834 -
RI18lto3 Net - - 0.288 - 2
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 C In - 8.123 -
uartrec.count_bit_4.resyn_0.uartrec.RI18lto3 OA1 Y Out 0.497 8.620 -
RI18 Net - - 0.602 - 3
uartrec.count_bit_4.resyn_0.uartrec.RI_2_sqmuxa NOR3A C In - 9.222 -
uartrec.count_bit_4.resyn_0.uartrec.RI_2_sqmuxa NOR3A Y Out 0.479 9.701 -
RI_2_sqmuxa Net - - 0.240 - 1
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A S In - 9.941 -
uartrec.count_bit_4.resyn_0.uartrec.RI_5 MX2A Y Out 0.358 10.299 -
RI_5 Net - - 0.240 - 1
uartrec.RI DFN1E0 D In - 10.539 -
=====================================================================================================================
Total path delay (propagation time + setup) of 10.942 is 5.535(50.6%) logic and 5.406(49.4%) route.
Path information for path number 3:
Requested Period: 10.000
- Setup time: 0.402
= Required time: 9.598
- Propagation time: 10.124
= Slack (non-critical) : -0.526
Number of logic level(s): 9
Starting point: uartrec.count[0] / Q
Ending point: uartrec.RI / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
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