stdout.log

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· LOG 代码 · 共 46 行

License checkout: synplifypro

Starting:    D:\Libero\Synplify\synplify_902A2\bin\mbin\synplify.exe
Install:     D:\Libero\Synplify\synplify_902A2
Date:        Tue Aug 19 09:08:53 2008
Version:     9.0.2A2


Arguments:   -product synplify_pro uart_test_syn.prj
ProductType: synplify_pro

License checkout: synplifypro
License: synplifypro node-locked 



Running synthesis on uart_test_syn:synthesis

log file: "E:\programer_new\UART\project\synthesis\uart_test.srr"


Running Verilog Compiler...

Verilog Compiler Completed


Running Analysis Property Generator...

Launching mapper in pro mode

Analysis Property Generator Completed


Analysis Property Generator Complete

Running ProASIC3 Mapper...

Launching mapper in pro mode

ProASIC3 Mapper Completed


exit status=0