uart_test.tlg

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

Selecting top level module uart_test
@N: CG364 :"E:\programer_new\UART\project\hdl\rec.v":20:7:20:9|Synthesizing module rec

@W: CL170 :"E:\programer_new\UART\project\hdl\rec.v":74:0:74:5|Pruning bit <9> of UartBuff[9:0] - not in use ...

@N: CG364 :"E:\programer_new\UART\project\hdl\send.v":20:7:20:10|Synthesizing module send

@W: CG133 :"E:\programer_new\UART\project\hdl\send.v":36:22:36:31|No assignment to datainbuf2
@N: CG364 :"E:\programer_new\UART\project\hdl\uart_test.v":20:7:20:15|Synthesizing module uart_test

@W: CS148 :"E:\programer_new\UART\project\hdl\uart_test.v":57:6:57:12|Undriven input rst, tying to 0
@W: CS148 :"E:\programer_new\UART\project\hdl\uart_test.v":65:7:65:14|Undriven input rst, tying to 0
@W: CG360 :"E:\programer_new\UART\project\hdl\uart_test.v":35:9:35:15|No assignment to wire clk100M

@W: CL189 :"E:\programer_new\UART\project\hdl\send.v":67:0:67:5|Register bit datainbuf[0] is always 0, optimizing ...
@W: CL171 :"E:\programer_new\UART\project\hdl\send.v":67:0:67:5|Pruning Register bit <0> of datainbuf[9:0]