uart_test.edn

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· EDN 代码 · 共 1,552 行 · 第 1/5 页

 )
           (port C (direction INPUT)
 )
         )
        (property is_combinational (integer 1))
       )
    )
    (cell NOR3 (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!(A + B + C)"))
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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           (port C (direction INPUT)
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         )
        (property is_combinational (integer 1))
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       (view prim (viewType NETLIST)
         (interface
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           (property function (string "!(!A + !B)"))
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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    (cell NOR2A (cellType GENERIC)
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       (view prim (viewType NETLIST)
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           (property function (string "!(!A + B)"))
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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    (cell NOR2 (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!(A + B)"))
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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         )
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    (cell MX2C (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "(!A & !S) + (!B & S)"))
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           (port B (direction INPUT)
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           (port S (direction INPUT)
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       (view prim (viewType NETLIST)
         (interface
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           (port B (direction INPUT)
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           (port B (direction INPUT)
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    (cell MAJ3 (cellType GENERIC)
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       (view prim (viewType NETLIST)
         (interface
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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           (port C (direction INPUT)
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         (interface
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           (port CLK (direction INPUT)
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           (port D (direction INPUT)
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           (port E (direction INPUT)
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        (property is_ff (integer 1))
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           (port D (direction INPUT)
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           (port E (direction INPUT)
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       (view prim (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT)
           (property function (string "IQ"))
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           (port CLK (direction INPUT)
           (property clock (integer 1))
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           (port D (direction INPUT)
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        (property is_ff (integer 1))
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      (property pad_cell (string "true"))
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           (port PAD (direction INPUT)
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      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "A"))
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           (port A (direction INPUT)
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        (property is_combinational (integer 1))
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    (cell AX1E (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!((A & B) ^ C)"))
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           (port B (direction INPUT)
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           (port C (direction INPUT)
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        (property is_combinational (integer 1))
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      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "(A & B) ^ C"))
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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           (port C (direction INPUT)
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        (property is_combinational (integer 1))
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    (cell AOI1 (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!(A & B + C)"))
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           (port A (direction INPUT)
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           (port B (direction INPUT)
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           (port C (direction INPUT)
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         )
        (property is_combinational (integer 1))
       )
    )
    (cell AO1D (cellType GENERIC)