uart_test.edn

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

(edif uart_test
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2008 8 19 9 9 1)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "Version 9.0.2A2, mapper 9.0.2, Build 065R"))
     )
   )
  (library PA3
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    (technology (numberDefinition ))
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        (property is_combinational (integer 1))
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    )
    (cell XNOR2 (cellType GENERIC)
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