uart_test_sdc.sdc

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· SDC 代码 · 共 26 行

# Top Level Design Parameters

# Clocks

create_clock -period 10.000000 -waveform {0.000000 5.000000} clock

# False Paths Between Clocks


# False Path Constraints


# Maximum Delay Constraints


# Multicycle Constraints


# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top

# Other Constraints