uart_test.so

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

<?xml version="1.0" encoding="UTF-8" ?>
<SynplifyOutput>
	<result>Success</result>
	<design>uart_test</design>
	<target_edif>E:\programer_new\UART\project\synthesis\uart_test.edn</target_edif>
</SynplifyOutput>