📄 uart_test.srr
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Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.428
= Required time: 9.572
- Propagation time: 0.839
= Slack (non-critical) : 8.733
Number of logic level(s): 0
Starting point: WR_R1 / Q
Ending point: WR_R2 / D
The start point is clocked by send|clkout_inferred_clock [rising] on pin CLK
The end point is clocked by send|clkout_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
WR_R1 DFN1 Q Out 0.550 0.550 -
WR_R1 Net - - 0.288 - 2
WR_R2 DFN1 D In - 0.839 -
=============================================================================
Total path delay (propagation time + setup) of 1.267 is 0.979(77.2%) logic and 0.288(22.8%) route.
====================================
Detailed Report for Clock: uart_test|clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
uartrec.cnt[5] uart_test|clock DFN1 Q cnt[5] 0.550 1.886
uartrec.cnt[7] uart_test|clock DFN1 Q cnt[7] 0.550 2.061
uartrec.cnt[6] uart_test|clock DFN1 Q cnt[6] 0.550 2.164
uartrec.cnt[11] uart_test|clock DFN1 Q cnt[11] 0.550 2.231
uartsend.cnt[0] uart_test|clock DFN1 Q cnt[0] 0.550 2.433
uartrec.cnt[1] uart_test|clock DFN1 Q cnt[1] 0.550 2.495
uartsend.cnt[1] uart_test|clock DFN1 Q cnt[1] 0.550 2.517
uartsend.cnt[4] uart_test|clock DFN1 Q cnt[4] 0.550 2.549
uartsend.cnt[9] uart_test|clock DFN1 Q cnt[9] 0.550 2.573
uartrec.cnt[0] uart_test|clock DFN1 Q cnt[0] 0.434 2.585
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------
uartrec.StartF uart_test|clock DFN1 D StartF_1 9.598 1.886
uartrec.count_bit[0] uart_test|clock DFN1E0 E un1_rst 9.546 2.107
uartrec.count_bit[1] uart_test|clock DFN1E0 E un1_rst 9.546 2.107
uartrec.count_bit[2] uart_test|clock DFN1E0 E un1_rst 9.546 2.107
uartrec.count_bit[3] uart_test|clock DFN1E0 E un1_rst 9.546 2.107
uartrec.count[0] uart_test|clock DFN1E1 E counte 9.546 2.229
uartrec.count[1] uart_test|clock DFN1E1 E counte 9.546 2.229
uartrec.count[2] uart_test|clock DFN1E1 E counte 9.546 2.229
uartrec.count[3] uart_test|clock DFN1E1 E counte 9.546 2.229
uartrec.cnt[12] uart_test|clock DFN1 D cnt_n12 9.598 2.495
===============================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.402
= Required time: 9.598
- Propagation time: 7.712
= Slack (critical) : 1.885
Number of logic level(s): 6
Starting point: uartrec.cnt[5] / Q
Ending point: uartrec.StartF / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------
uartrec.cnt[5] DFN1 Q Out 0.550 0.550 -
cnt[5] Net - - 1.063 - 6
uartrec.clkout_12_3 NOR2A A In - 1.613 -
uartrec.clkout_12_3 NOR2A Y Out 0.469 2.082 -
clkout_12_3 Net - - 0.240 - 1
uartrec.clkout_12_5 NOR3A A In - 2.322 -
uartrec.clkout_12_5 NOR3A Y Out 0.479 2.801 -
clkout_12_5 Net - - 0.240 - 1
uartrec.clkout_12 OR2B A In - 3.041 -
uartrec.clkout_12 OR2B Y Out 0.384 3.425 -
clkout_12 Net - - 0.884 - 4
uartrec.clkout OR2 A In - 4.309 -
uartrec.clkout OR2 Y Out 0.271 4.580 -
clkrec Net - - 1.489 - 12
uartrec.StartF_0 OA1 B In - 6.069 -
uartrec.StartF_0 OA1 Y Out 0.674 6.743 -
N_116 Net - - 0.240 - 1
uartrec.StartF_1 AO1D C In - 6.983 -
uartrec.StartF_1 AO1D Y Out 0.489 7.472 -
StartF_1 Net - - 0.240 - 1
uartrec.StartF DFN1 D In - 7.712 -
===================================================================================
Total path delay (propagation time + setup) of 8.114 is 3.718(45.8%) logic and 4.396(54.2%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell uart_test.verilog
Core Cell usage:
cell count area count*area
AND2 1 1.0 1.0
AND3 6 1.0 6.0
AO1 1 1.0 1.0
AO1C 1 1.0 1.0
AO1D 2 1.0 2.0
AOI1 3 1.0 3.0
AX1C 9 1.0 9.0
AX1E 6 1.0 6.0
BUFF 1 1.0 1.0
GND 3 0.0 0.0
INV 1 1.0 1.0
MAJ3 1 1.0 1.0
MX2 5 1.0 5.0
MX2A 1 1.0 1.0
MX2C 4 1.0 4.0
NOR2 15 1.0 15.0
NOR2A 12 1.0 12.0
NOR2B 24 1.0 24.0
NOR3 1 1.0 1.0
NOR3A 6 1.0 6.0
NOR3B 5 1.0 5.0
NOR3C 21 1.0 21.0
OA1 3 1.0 3.0
OA1B 1 1.0 1.0
OA1C 1 1.0 1.0
OR2 4 1.0 4.0
OR2A 10 1.0 10.0
OR2B 6 1.0 6.0
OR3B 1 1.0 1.0
OR3C 2 1.0 2.0
VCC 3 0.0 0.0
XA1 3 1.0 3.0
XA1A 1 1.0 1.0
XA1B 6 1.0 6.0
XA1C 7 1.0 7.0
XNOR2 1 1.0 1.0
XOR2 11 1.0 11.0
DFN1 46 1.0 46.0
DFN1E0 11 1.0 11.0
DFN1E1 24 1.0 24.0
----- ----------
TOTAL 270 264.0
IO Cell usage:
cell count
CLKBUF 1
INBUF 1
OUTBUF 1
-----
TOTAL 3
Core Cells : 264 of 768 (34%)
IO Cells : 3
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Aug 19 09:09:01 2008
###########################################################]
Total runtime: 00h:00m:05s realtime
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