uart_test.srr

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

#Build: Synplify Pro 9.0.2A2, Build 250R, Feb 20 2008
#install: D:\Libero\Synplify\synplify_902A2
#OS: Windows XP 5.1
#Hostname: BIMINGMING

#Implementation: synthesis

#Tue Aug 19 09:08:56 2008

$ Start of Compile
#Tue Aug 19 09:08:56 2008

Synplicity Verilog Compiler, version 1.0, Build 145R, built Mar  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v"
@I::"E:\programer_new\UART\project\hdl\rec.v"
@I::"E:\programer_new\UART\project\hdl\send.v"
@I::"E:\programer_new\UART\project\hdl\uart_test.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module uart_test
@N: CG364 :"E:\programer_new\UART\project\hdl\rec.v":20:7:20:9|Synthesizing module rec

@W: CL170 :"E:\programer_new\UART\project\hdl\rec.v":74:0:74:5|Pruning bit <9> of UartBuff[9:0] - not in use ...

@N: CG364 :"E:\programer_new\UART\project\hdl\send.v":20:7:20:10|Synthesizing module send

@W: CG133 :"E:\programer_new\UART\project\hdl\send.v":36:22:36:31|No assignment to datainbuf2
@N: CG364 :"E:\programer_new\UART\project\hdl\uart_test.v":20:7:20:15|Synthesizing module uart_test

@W: CS148 :"E:\programer_new\UART\project\hdl\uart_test.v":57:6:57:12|Undriven input rst, tying to 0
@W: CS148 :"E:\programer_new\UART\project\hdl\uart_test.v":65:7:65:14|Undriven input rst, tying to 0
@W: CG360 :"E:\programer_new\UART\project\hdl\uart_test.v":35:9:35:15|No assignment to wire clk100M

@W: CL189 :"E:\programer_new\UART\project\hdl\send.v":67:0:67:5|Register bit datainbuf[0] is always 0, optimizing ...
@W: CL171 :"E:\programer_new\UART\project\hdl\send.v":67:0:67:5|Pruning Register bit <0> of datainbuf[9:0] 

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug 19 09:08:56 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.2, Build 065R, Built Mar  5 2008 17:44:07
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0.2A2
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 41MB)
@N: MF238 :"e:\programer_new\uart\project\hdl\uart_test.v":54:16:54:28|Found 8 bit incrementor, 'senddata_1[7:0]'
@N:"e:\programer_new\uart\project\hdl\rec.v":74:0:74:5|Found counter in view:work.rec(verilog) inst count_bit[3:0]
@N:"e:\programer_new\uart\project\hdl\rec.v":74:0:74:5|Found counter in view:work.rec(verilog) inst count[3:0]
@N:"e:\programer_new\uart\project\hdl\rec.v":49:0:49:5|Found counter in view:work.rec(verilog) inst cnt[15:0]
@N:"e:\programer_new\uart\project\hdl\send.v":90:0:90:5|Found counter in view:work.send(verilog) inst bincnt[3:0]
@N:"e:\programer_new\uart\project\hdl\send.v":49:0:49:5|Found counter in view:work.send(verilog) inst cnt[15:0]

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 42MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 42MB peak: 42MB)
Promoting Net clock_c on CLKBUF  clock_pad
Buffering clksend, fanout 20 segments 2

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)

Added 1 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 41MB peak: 42MB)
Writing Analyst data base E:\programer_new\UART\project\synthesis\uart_test.srm
@N: BN225 |Writing default property annotation file E:\programer_new\UART\project\synthesis\uart_test.map.
Writing EDIF Netlist and constraint files
Version 9.0.2A2
Found clock uart_test|clock with period 10.00ns 
Found clock rec|RI_inferred_clock with period 10.00ns 
Found clock send|clkout_inferred_clock with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Aug 19 09:09:01 2008
#


Top view:               uart_test
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 1.886

                               Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                 Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------------------
send|clkout_inferred_clock     100.0 MHz     789.4 MHz     10.000        1.267         8.733     inferred     Inferred_clkgroup_2
uart_test|clock                100.0 MHz     123.2 MHz     10.000        8.114         1.886     inferred     Inferred_clkgroup_1
=================================================================================================================================





Clock Relationships
*******************

Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------
Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------
rec|RI_inferred_clock       uart_test|clock             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
uart_test|clock             rec|RI_inferred_clock       |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
uart_test|clock             uart_test|clock             |  10.000      1.886  |  No paths    -      |  No paths    -      |  No paths    -    
uart_test|clock             send|clkout_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
send|clkout_inferred_clock  uart_test|clock             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
send|clkout_inferred_clock  send|clkout_inferred_clock  |  10.000      8.733  |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: send|clkout_inferred_clock
====================================



Starting Points with Worst Slack
********************************

             Starting                                                  Arrival          
Instance     Reference                      Type     Pin     Net       Time        Slack
             Clock                                                                      
----------------------------------------------------------------------------------------
WR_R1        send|clkout_inferred_clock     DFN1     Q       WR_R1     0.550       8.733
WR_R2        send|clkout_inferred_clock     DFN1     Q       WR_R2     0.550       8.733
========================================================================================


Ending Points with Worst Slack
******************************

             Starting                                                  Required          
Instance     Reference                      Type     Pin     Net       Time         Slack
             Clock                                                                       
-----------------------------------------------------------------------------------------
WR_R2        send|clkout_inferred_clock     DFN1     D       WR_R1     9.572        8.733
WR_R3        send|clkout_inferred_clock     DFN1     D       WR_R2     9.572        8.733
=========================================================================================



Worst Path Information
***********************