sap.log

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· LOG 代码 · 共 13 行

Synplicity Proasic Technology Mapper, Version 9.0.2, Build 065R, Built Mar  5 2008 17:44:07
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0.2A2
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


@N: BN225 |Writing default property annotation file E:\programer_new\UART\project\synthesis\uart_test.sap.
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug 19 09:08:58 2008

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