uart_test.plg

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· PLG 代码 · 共 17 行

@P:  Worst Slack : 1.886
@P:  send|clkout_inferred_clock - Estimated Frequency : 789.4 MHz
@P:  send|clkout_inferred_clock - Requested Frequency : 100.0 MHz
@P:  send|clkout_inferred_clock - Estimated Period : 1.267
@P:  send|clkout_inferred_clock - Requested Period : 10.000
@P:  send|clkout_inferred_clock - Slack : 8.733
@P:  uart_test|clock - Estimated Frequency : 123.2 MHz
@P:  uart_test|clock - Requested Frequency : 100.0 MHz
@P:  uart_test|clock - Estimated Period : 8.114
@P:  uart_test|clock - Requested Period : 10.000
@P:  uart_test|clock - Slack : 1.886
@P:  Total Area : 264.0
@P:  Total Area : 100.0
@P:  Total Area : 135.0
@P:  Total Area : 264.0
@P:  CPU Time : 0h:00m:02s