uart_test_toc.htm

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· HTM 代码 · 共 21 行

HTM
21 行
字号 
<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap class="content" valign="top">
<body bgcolor="#e0e0ff">
<font size=3 face="arial">
<dl>
<font size=3><b>synthesis (uart_test)</b><br></font>
<b><a href="uart_test_srr.htm#compilerReport1" target="srrFrame">Compiler Report</a></b><br>
<b><a href="uart_test_srr.htm#timingReport2" target="srrFrame">Timing Report</a></b><br>
<a href="uart_test_srr.htm#performanceSummary3" target="srrFrame">Performance Summary</a><br>
<a href="uart_test_srr.htm#clockRelationships4" target="srrFrame">Clock Relationships</a><br>
<a href="uart_test_srr.htm#interfaceInfo5" target="srrFrame">Interface Information</a><br>
<a href="uart_test_srr.htm#clockReport6" target="srrFrame">Detailed Report for Clock: send|clkout_inferred_clock</a><br>
&nbsp;&nbsp;&nbsp;<a href="uart_test_srr.htm#startingSlack7" target="srrFrame">Starting Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="uart_test_srr.htm#endingSlack8" target="srrFrame">Ending Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="uart_test_srr.htm#worstPaths9" target="srrFrame">Worst Path Information</a><br>
<a href="uart_test_srr.htm#clockReport10" target="srrFrame">Detailed Report for Clock: uart_test|clock</a><br>
&nbsp;&nbsp;&nbsp;<a href="uart_test_srr.htm#startingSlack11" target="srrFrame">Starting Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="uart_test_srr.htm#endingSlack12" target="srrFrame">Ending Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="uart_test_srr.htm#worstPaths13" target="srrFrame">Worst Path Information</a><br>

uart_test_toc.htm - 源码说明

本页面展示了「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」中的 uart_test_toc.htm 源码文件，采用 HTM 编程语言编写，共 21 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫下载站收录了大量与Verilog相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?