smartgen.aws

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><workspace xmlns="http://actel.com/sweng/afi"><name>smartgen</name><netlistFormat>Verilog</netlistFormat><reports><resource select="T"/></reports><subproject libero="T"/><hdltype>Verilog</hdltype><componentInstances/><device die="IQ2X1M0" family="ProASIC3" package="vq100"/><SmartGen version="8.0"/></workspace>