uart.prj

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "D:\Actelprj\USB\0417\hdl"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "IQ2X1M0"
KEY VendorTechnology_Package "vq100"
KEY ProjectLocation "E:\programer_new\UART\project"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "uart_test::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\designer\impl1\uart_test.adb,adb"
STATE="utd"
TIME="1219038750"
SIZE="189952"
ENDFILE
VALUE "<project>\designer\impl1\uart_test.pdb,pdb"
STATE="utd"
TIME="1219038728"
SIZE="17408"
ENDFILE
VALUE "<project>\designer\impl1\uart_test_fp\uart_test.pro,pro"
STATE="utd"
TIME="1219041887"
SIZE="1563"
ENDFILE
VALUE "<project>\hdl\rec.v,hdl"
STATE="utd"
TIME="1219108124"
SIZE="3698"
ENDFILE
VALUE "<project>\hdl\send.v,hdl"
STATE="utd"
TIME="1219108128"
SIZE="3535"
ENDFILE
VALUE "<project>\hdl\uart_test.v,hdl"
STATE="utd"
TIME="1219108126"
SIZE="2460"
ENDFILE
VALUE "<project>\synthesis\uart_test.edn,syn_edn"
STATE="utd"
TIME="1219038650"
SIZE="118401"
ENDFILE
VALUE "<project>\synthesis\uart_test_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1219038650"
SIZE="378"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "uart_test::work"
FILE "<project>\hdl\uart_test.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\uart_test.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\uart_test.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\uart_test.edn,syn_edn"
VALUE "<project>\synthesis\uart_test_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\uart_test.v,syn_hdl"
VALUE "<project>\phy_synthesis\uart_test_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\uart_test_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\uart_test_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\uart_test_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\uart_test_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\uart_test.adb,adb"
VALUE "<project>\designer\impl1\uart_test.prb,prb"
VALUE "<project>\designer\impl1\uart_test.stp,stp"
VALUE "<project>\designer\impl1\uart_test_fp\uart_test.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=C:\Core2Console_v1.4\bin\CoreConsole.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=D:\Libero\Synplify\synplify_902A2\bin\synplify_pro.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=D:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=D:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=D:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "uart_test::work"
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\uart_test.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\uart_test.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\uart_test.edn,syn_edn"
VALUE "<project>\synthesis\uart_test_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\uart_test.v,syn_hdl"
VALUE "<project>\phy_synthesis\uart_test_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\uart_test_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\uart_test_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\uart_test_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\uart_test_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\uart_test.adb,adb"
VALUE "<project>\designer\impl1\uart_test.prb,prb"
VALUE "<project>\designer\impl1\uart_test.stp,stp"
VALUE "<project>\designer\impl1\uart_test_fp\uart_test.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\hdl\rec.v,hdl
FILE:<project>\hdl\uart_test.v,hdl
FILE:<project>\hdl\send.v,hdl
FILE:<project>\synthesis\uart_test.edn,syn_edn
ACTIVE_VIEW:0
ENDLIST