cnt2.tan.rpt

来自「对输入时钟做除以8的分频和除以4的分频功能」· RPT 代码 · 共 179 行

Timing Analyzer report for CNT2
Sat Apr 01 11:25:25 2006
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tco
  7. Minimum tco
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
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to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
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intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
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licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-----------------------------------------------------------------------------------------
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C3T100C6        ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-----------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                         ;
+------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                                    ; From  ; To    ;
+------------------------+-------+---------------+------------------------------------------------+-------+-------+
; Worst-case tco         ; N/A   ; None          ; 4.804 ns                                       ; HH[2] ; Q9    ;
; Worst-case minimum tco ; N/A   ; None          ; 4.802 ns                                       ; HH[1] ; Q8    ;
; Clock Setup: 'CLK'     ; N/A   ; None          ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[2] ; HH[2] ;
+------------------------+-------+---------------+------------------------------------------------+-------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                 ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period)                           ; From  ; To    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[2] ; HH[2] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[1] ; HH[2] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[1] ; HH[1] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[0] ; HH[1] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[0] ; HH[2] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; HH[0] ; HH[0] ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------+
; tco                                                         ;
+--------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From  ; To ; From Clock ;
+-------+--------------+------------+-------+----+------------+
; N/A   ; None         ; 4.804 ns   ; HH[2] ; Q9 ; CLK        ;
; N/A   ; None         ; 4.802 ns   ; HH[1] ; Q8 ; CLK        ;
+-------+--------------+------------+-------+----+------------+


+-----------------------------------------------------------------------------+
; Minimum tco                                                                 ;
+------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From  ; To ; From Clock ;
+---------------+------------------+----------------+-------+----+------------+
; N/A           ; None             ; 4.802 ns       ; HH[1] ; Q8 ; CLK        ;
; N/A           ; None             ; 4.804 ns       ; HH[2] ; Q9 ; CLK        ;
+---------------+------------------+----------------+-------+----+------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Apr 01 11:25:25 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off CNT2 -c CNT2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
Info: Clock CLK Internal fmax is restricted to 405.19 MHz between source register HH[2] and destination register HH[2]
    Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.851 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH[2]'
            Info: 2: + IC(0.384 ns) + CELL(0.467 ns) = 0.851 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH[2]'
            Info: Total cell delay = 0.467 ns ( 54.88 % )
            Info: Total interconnect delay = 0.384 ns ( 45.12 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock CLK to destination register is 2.121 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH[2]'
                Info: Total cell delay = 1.677 ns ( 79.07 % )
                Info: Total interconnect delay = 0.444 ns ( 20.93 % )
            Info: - Longest clock path from clock CLK to source register is 2.121 ns
                Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH[2]'
                Info: Total cell delay = 1.677 ns ( 79.07 % )
                Info: Total interconnect delay = 0.444 ns ( 20.93 % )
        Info: + Micro clock to output delay of source is 0.173 ns
        Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock CLK to destination pin Q9 through register HH[2] is 4.804 ns
    Info: + Longest clock path from clock CLK to source register is 2.121 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH[2]'
        Info: Total cell delay = 1.677 ns ( 79.07 % )
        Info: Total interconnect delay = 0.444 ns ( 20.93 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.510 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH[2]'
        Info: 2: + IC(0.876 ns) + CELL(1.634 ns) = 2.510 ns; Loc. = Pin_69; Fanout = 0; PIN Node = 'Q9'
        Info: Total cell delay = 1.634 ns ( 65.10 % )
        Info: Total interconnect delay = 0.876 ns ( 34.90 % )
Info: Minimum tco from clock CLK to destination pin Q8 through register HH[1] is 4.802 ns
    Info: + Shortest clock path from clock CLK to source register is 2.121 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N2; Fanout = 3; REG Node = 'HH[1]'
        Info: Total cell delay = 1.677 ns ( 79.07 % )
        Info: Total interconnect delay = 0.444 ns ( 20.93 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Shortest register to pin delay is 2.508 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N2; Fanout = 3; REG Node = 'HH[1]'
        Info: 2: + IC(0.874 ns) + CELL(1.634 ns) = 2.508 ns; Loc. = Pin_70; Fanout = 0; PIN Node = 'Q8'
        Info: Total cell delay = 1.634 ns ( 65.15 % )
        Info: Total interconnect delay = 0.874 ns ( 34.85 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Apr 01 11:25:25 2006
    Info: Elapsed time: 00:00:00