📄 cnt2.csf.qmsg
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 11:25:21 2006 " "Info: Processing ended: Sat Apr 01 11:25:21 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0} } { } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 11:25:23 2006 " "Info: Processing started: Sat Apr 01 11:25:23 2006" { } { } 0} } { } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off CNT2 -c CNT2 " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off CNT2 -c CNT2" { } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 11:25:24 2006 " "Info: Processing ended: Sat Apr 01 11:25:24 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 11:25:25 2006 " "Info: Processing started: Sat Apr 01 11:25:25 2006" { } { } 0} } { } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off CNT2 -c CNT2 --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off CNT2 -c CNT2 --timing_analysis_only" { } { } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" { } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register HH\[2\] HH\[2\] 405.19 MHz Internal " "Info: Clock CLK Internal fmax is restricted to 405.19 MHz between source register HH\[2\] and destination register HH\[2\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.851 ns + Longest register register " "Info: + Longest register to register delay is 0.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HH\[2\] 1 REG LC_X26_Y9_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH\[2\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.467 ns) 0.851 ns HH\[2\] 2 REG LC_X26_Y9_N8 2 " "Info: 2: + IC(0.384 ns) + CELL(0.467 ns) = 0.851 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH\[2\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.851 ns" { HH[2] HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.467 ns 54.88 % " "Info: Total cell delay = 0.467 ns ( 54.88 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.384 ns 45.12 % " "Info: Total interconnect delay = 0.384 ns ( 45.12 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.851 ns" { HH[2] HH[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.121 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_10 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.547 ns) 2.121 ns HH\[2\] 2 REG LC_X26_Y9_N8 2 " "Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH\[2\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.991 ns" { CLK HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.07 % " "Info: Total cell delay = 1.677 ns ( 79.07 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns 20.93 % " "Info: Total interconnect delay = 0.444 ns ( 20.93 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.121 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_10 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.547 ns) 2.121 ns HH\[2\] 2 REG LC_X26_Y9_N8 2 " "Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH\[2\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.991 ns" { CLK HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.07 % " "Info: Total cell delay = 1.677 ns ( 79.07 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns 20.93 % " "Info: Total interconnect delay = 0.444 ns ( 20.93 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.851 ns" { HH[2] HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q9 HH\[2\] 4.804 ns register " "Info: tco from clock CLK to destination pin Q9 through register HH\[2\] is 4.804 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.121 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_10 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.547 ns) 2.121 ns HH\[2\] 2 REG LC_X26_Y9_N8 2 " "Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH\[2\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.991 ns" { CLK HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.07 % " "Info: Total cell delay = 1.677 ns ( 79.07 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns 20.93 % " "Info: Total interconnect delay = 0.444 ns ( 20.93 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.510 ns + Longest register pin " "Info: + Longest register to pin delay is 2.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HH\[2\] 1 REG LC_X26_Y9_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N8; Fanout = 2; REG Node = 'HH\[2\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(1.634 ns) 2.510 ns Q9 2 PIN Pin_69 0 " "Info: 2: + IC(0.876 ns) + CELL(1.634 ns) = 2.510 ns; Loc. = Pin_69; Fanout = 0; PIN Node = 'Q9'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.510 ns" { HH[2] Q9 } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 23 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 65.10 % " "Info: Total cell delay = 1.634 ns ( 65.10 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.876 ns 34.90 % " "Info: Total interconnect delay = 0.876 ns ( 34.90 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.510 ns" { HH[2] Q9 } "NODE_NAME" } } } } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[2] } "NODE_NAME" } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.510 ns" { HH[2] Q9 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK Q8 HH\[1\] 4.802 ns register " "Info: Minimum tco from clock CLK to destination pin Q8 through register HH\[1\] is 4.802 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.121 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK 1 CLK Pin_10 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = Pin_10; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.547 ns) 2.121 ns HH\[1\] 2 REG LC_X26_Y9_N2 3 " "Info: 2: + IC(0.444 ns) + CELL(0.547 ns) = 2.121 ns; Loc. = LC_X26_Y9_N2; Fanout = 3; REG Node = 'HH\[1\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.991 ns" { CLK HH[1] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.07 % " "Info: Total cell delay = 1.677 ns ( 79.07 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns 20.93 % " "Info: Total interconnect delay = 0.444 ns ( 20.93 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.508 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HH\[1\] 1 REG LC_X26_Y9_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N2; Fanout = 3; REG Node = 'HH\[1\]'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { HH[1] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(1.634 ns) 2.508 ns Q8 2 PIN Pin_70 0 " "Info: 2: + IC(0.874 ns) + CELL(1.634 ns) = 2.508 ns; Loc. = Pin_70; Fanout = 0; PIN Node = 'Q8'" { } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.508 ns" { HH[1] Q8 } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 23 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 65.15 % " "Info: Total cell delay = 1.634 ns ( 65.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.874 ns 34.85 % " "Info: Total interconnect delay = 0.874 ns ( 34.85 % )" { } { } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.508 ns" { HH[1] Q8 } "NODE_NAME" } } } } 0} } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.121 ns" { CLK HH[1] } "NODE_NAME" } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "2.508 ns" { HH[1] Q8 } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 11:25:25 2006 " "Info: Processing ended: Sat Apr 01 11:25:25 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0} } { } 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1 " "Info: Quartus II Full Compilation was successful. 0 errors, 1 warning" { } { } 0}
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