cnt2.csf.qmsg

对输入时钟做除以8的分频和除以4的分频功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 11:25:08 2006 " "Info: Processing started: Sat Apr 01 11:25:08 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off CNT2 -c CNT2 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off CNT2 -c CNT2" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "CNT2.vhd 2 1 " "Info: Using design file CNT2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT2-CNTT " "Info: Found design unit 1: CNT2-CNTT" {  } { { "d:/cpld/cnt/CNT2.vhd" "CNT2-CNTT" "" { Text "d:/cpld/cnt/CNT2.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT2 " "Info: Found entity 1: CNT2" {  } { { "d:/cpld/cnt/CNT2.vhd" "CNT2" "" { Text "d:/cpld/cnt/CNT2.vhd" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "3 " "Info: Implemented 3 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 11:25:11 2006 " "Info: Processing ended: Sat Apr 01 11:25:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 11:25:13 2006 " "Info: Processing started: Sat Apr 01 11:25:13 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off CNT2 -c CNT2 " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off CNT2 -c CNT2" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "CNT2 EP1C3T100C6 " "Info: Automatically selected device EP1C3T100C6 for design CNT2" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " {  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 4 " "Info: No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q8 " "Info: Pin Q8 not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 23 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Q8" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { Q8 } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { Q8 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q9 " "Info: Pin Q9 not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 23 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Q9" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { Q9 } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { Q9 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { CLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLR } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { CLR } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_PERIOD_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on non-logic cell registers with location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in Pin 10 " "Info: Automatically promoted signal CLK to use Global clock in Pin 10" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLR Global clock in Pin 66 " "Info: Automatically promoted signal CLR to use Global clock in Pin 66" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}