cnt2.fit.qmsg

对输入时钟做除以8的分频和除以4的分频功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 11:25:13 2006 " "Info: Processing started: Sat Apr 01 11:25:13 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off CNT2 -c CNT2 " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off CNT2 -c CNT2" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "CNT2 EP1C3T100C6 " "Info: Automatically selected device EP1C3T100C6 for design CNT2" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " {  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 4 " "Info: No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q8 " "Info: Pin Q8 not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 23 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Q8" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { Q8 } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { Q8 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Q9 " "Info: Pin Q9 not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 23 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Q9" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { Q9 } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { Q9 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { CLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } } { "d:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "d:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { CLR } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.fld" "" "" { Floorplan "d:/cpld/cnt/CNT2.fld" "" "" { CLR } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_PERIOD_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on non-logic cell registers with location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in Pin 10 " "Info: Automatically promoted signal CLK to use Global clock in Pin 10" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLR Global clock in Pin 66 " "Info: Automatically promoted signal CLR to use Global clock in Pin 66" {  } { { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 22 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP Scan-chain Inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF " "Info: Statistics of I/O pins that use the same VCCIO and VREF" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.30 0 2 0 " "Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 0 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 16 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 5 9 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  9 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 16 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.712 ns register register " "Info: Estimated most critical path is register to register delay of 0.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HH\[0\] 1 REG LAB_X26_Y9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y9; Fanout = 3; REG Node = 'HH\[0\]'" {  } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "" { HH[0] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.238 ns) 0.712 ns HH\[1\] 2 REG LAB_X26_Y9 3 " "Info: 2: + IC(0.474 ns) + CELL(0.238 ns) = 0.712 ns; Loc. = LAB_X26_Y9; Fanout = 3; REG Node = 'HH\[1\]'" {  } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.712 ns" { HH[0] HH[1] } "NODE_NAME" } } } { "d:/cpld/cnt/CNT2.vhd" "" "" { Text "d:/cpld/cnt/CNT2.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.238 ns 33.43 % " "Info: Total cell delay = 0.238 ns ( 33.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.474 ns 66.57 % " "Info: Total interconnect delay = 0.474 ns ( 66.57 % )" {  } {  } 0}  } { { "d:/cpld/cnt/db/CNT2_cmp.qrpt" "" "" { Report "d:/cpld/cnt/db/CNT2_cmp.qrpt" Compiler "CNT2" "UNKNOWN" "V1" "d:/cpld/cnt/db/CNT2.quartus_db" { Floorplan "" "" "0.712 ns" { HH[0] HH[1] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 11:25:21 2006 " "Info: Processing ended: Sat Apr 01 11:25:21 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}