📄 cnt2.fit.rpt
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+---------------------------------------------------------------------------------------------+
; Control Signals ;
+----------------------------------------------------------------------------------------------
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------+----------+---------+--------------+--------+----------------------+------------------+
; CLK ; Pin_10 ; 3 ; Clock ; yes ; Global clock ; GCLK2 ;
; CLR ; Pin_66 ; 3 ; Async. clear ; yes ; Global clock ; GCLK6 ;
+------+----------+---------+--------------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+----------------------------------------------------------------------
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; CLK ; Pin_10 ; 3 ; Global clock ; GCLK2 ;
; CLR ; Pin_66 ; 3 ; Global clock ; GCLK6 ;
+------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------------------
; Name ; Fan-Out ;
+-------+-------------------------+
; HH[0] ; 3 ;
; HH[1] ; 3 ;
; HH[2] ; 2 ;
+-------+-------------------------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------------------------------
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 0 / 8,840 ( 0 % ) ;
; Direct links ; 2 / 11,506 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; LAB clocks ; 2 / 156 ( 1 % ) ;
; LUT chains ; 0 / 2,619 ( 0 % ) ;
; Local interconnects ; 2 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 0 / 7,520 ( 0 % ) ;
+----------------------------+----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 3.00) ; Number of LABs (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 1 ;
; 1 Clock ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 3.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 2.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 2.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
+---------------------------------------------+-----------------------------+
+------------------+
; Fitter Messages ;
+------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
Info: Processing started: Sat Apr 01 11:25:13 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off CNT2 -c CNT2
Info: Automatically selected device EP1C3T100C6 for design CNT2
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: No exact pin location assignment(s) for 4 pins of 4 total pins
Info: Pin Q8 not assigned to an exact location on the device
Info: Pin Q9 not assigned to an exact location on the device
Info: Pin CLK not assigned to an exact location on the device
Info: Pin CLR not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency
Info: Performing register packing on non-logic cell registers with location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal CLK to use Global clock in Pin 10
Info: Automatically promoted signal CLR to use Global clock in Pin 66
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP Scan-chain Inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF
Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 0 input, 2 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 11 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 16 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: Details of I/O bank after I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used -- 9 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 16 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 0.712 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y9; Fanout = 3; REG Node = 'HH[0]'
Info: 2: + IC(0.474 ns) + CELL(0.238 ns) = 0.712 ns; Loc. = LAB_X26_Y9; Fanout = 3; REG Node = 'HH[1]'
Info: Total cell delay = 0.238 ns ( 33.43 % )
Info: Total interconnect delay = 0.474 ns ( 66.57 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Apr 01 11:25:21 2006
Info: Elapsed time: 00:00:08
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