cnt2.vhd

对输入时钟做除以8的分频和除以4的分频功能

-- DPC R&D High Voltage Inverter Design Version 0.6-----------------------------------------
--  FILE NAME	:	cnt2.vhd
--  PROJECT		:	HVF PWM Make and Fiber communication
--  PURPOSE		:	This file contains the entity and architecture 
--					for the top level of the pwm design.
--  Author      :   Shen Shi Jun 
--  Date        :   9/9/2004
--Copyright 2004 DPC Corporation. All rights reserved.  DPC products are
--protected under numerous CHINA. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.  
--
--------------------------------------------------------
--Function description
-- Clock frequency divide
-- 8 divide frequency
----------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity CNT2 is
PORT(
     CLR,CLK:IN STD_LOGIC;
     Q8,Q9: OUT STD_LOGIC);

end;

architecture CNTT of CNT2 is
 SIGNAL  GG: STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
    Q8<= GG(1);
	Q9<= GG(2);
   PROCESS(CLK,CLR)
   VARIABLE   HH: INTEGER RANGE 0 TO 7;
     BEGIN
       IF(CLR='0') THEN
            HH:=0;
          ELSIF CLK'EVENT AND CLK='1' THEN
               IF HH=7 THEN
                  HH:=0;
               ELSE
                  HH:= HH + 1;
               END IF;
           END IF;
         GG<= CONV_STD_LOGIC_VECTOR(HH,3);
      END PROCESS;

end CNTT;