code_dco.v

通信电路中产生扩频码的电路

`timescale 1ns/1ps
module code_dco(in_corrclk                 ,
                hd_rstn                 ,
                sf_rstn                   ,
                in_mod_sel                 ,
                in_tic                     ,
                in_epoch_cnt_load_written  ,
                in_dump                    ,
                f_control           ,
                in_CODE_DCO_PRESET_PHASE   ,
                out_next_ca_code           ,
                code_nco_phase
                
                );

input in_corrclk ;     //39MHz
input hd_rstn ;
input sf_rstn;
input in_mod_sel; //0:update 1:preset
input in_tic;
input in_epoch_cnt_load_written;
input in_dump;
input [27:0] f_control;
input [7:0] in_CODE_DCO_PRESET_PHASE;

output out_next_ca_code;
output [9:0] code_nco_phase;

reg [28:0] code_dco_incr;
reg [29:0] code_dco_acc;
reg code_dco_acc_msb_dly;

//wire config_valid;
wire tmp1;

//generate config_valid signal 
//if config_valid == 1, control information from the register file is valid
//assign config_valid = in_mod_sel ? (in_tic && in_epoch_cnt_load_written) : in_dump;

always @(posedge in_corrclk or negedge hd_rstn)
  if(!hd_rstn)
    code_dco_incr <= 28'h0fffff0;
  else
    if(in_dump)
      code_dco_incr <= {1'b0,f_control};

//acc increment code_dco_incr every corrclk cycle
//if tic is set at preset mode ,the bit [27:20] of code_dco_acc
//is padded with register file and the lower bits are padded with zeros

assign tmp1 = in_mod_sel && in_tic && in_epoch_cnt_load_written;

always @(posedge in_corrclk or negedge hd_rstn or negedge sf_rstn)
  //if(!hd_rstn || !sf_rstn)
  if(!hd_rstn)
    code_dco_acc <= 29'b0;
  else
    if(!sf_rstn)
      code_dco_acc <= 29'b0;
    else
      if(tmp1)
        code_dco_acc[27:0] <= {in_CODE_DCO_PRESET_PHASE,20'b0};
      else
        code_dco_acc <= code_dco_acc + code_dco_incr;

//delay the msb of code_dco_acc by 1 clock cycle for overflow generation
always @(posedge in_corrclk or negedge hd_rstn)
  if(!hd_rstn)
    code_dco_acc_msb_dly <= 1'b0;
  else
    code_dco_acc_msb_dly <= code_dco_acc[29];

//if the msb of code_dco_acc changes during 1 cycle ,the out_next_ca_code is set
assign out_next_ca_code = code_dco_acc_msb_dly ^ code_dco_acc[29];

//output the bits[27:18] of code_dco_acc to the register file for code dco phase
//and in the register file the phase is latched when the next tic signal comes
assign code_nco_phase = code_dco_acc[28:19];

endmodule