poc_printer.map.qmsg

用VHDL语言讲述输出控制器（POC）的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 08 23:37:49 2009 " "Info: Processing started: Sun Mar 08 23:37:49 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off POC_PRINTER -c POC_PRINTER " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off POC_PRINTER -c POC_PRINTER" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "POC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file POC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 POC-BEHAVE " "Info: Found design unit 1: POC-BEHAVE" {  } { { "POC.vhd" "" { Text "D:/shiy/POC.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 POC " "Info: Found entity 1: POC" {  } { { "POC.vhd" "" { Text "D:/shiy/POC.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PRINTER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PRINTER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PRINTER-BEHAVE " "Info: Found design unit 1: PRINTER-BEHAVE" {  } { { "PRINTER.vhd" "" { Text "D:/shiy/PRINTER.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PRINTER " "Info: Found entity 1: PRINTER" {  } { { "PRINTER.vhd" "" { Text "D:/shiy/PRINTER.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "POC_PRINTER.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file POC_PRINTER.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 POC_PRINTER " "Info: Found entity 1: POC_PRINTER" {  } { { "POC_PRINTER.bdf" "" { Schematic "D:/shiy/POC_PRINTER.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PRINTER " "Info: Elaborating entity \"PRINTER\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Error" "EVRFX_GENERIC_ERROR_WITH_LOC" "can't infer register for RDY because its behavior does not match a known template PRINTER.vhd(15) " "Error (10001): Verilog HDL or VHDL error at PRINTER.vhd(15): can't infer register for RDY because its behavior does not match a known template" {  } { { "PRINTER.vhd" "" { Text "D:/shiy/PRINTER.vhd" 15 0 0 } }  } 0 10001 "Verilog HDL or VHDL error at %2!s!: %1!s!" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "RDY PRINTER.vhd(13) " "Info (10041): Verilog HDL or VHDL info at PRINTER.vhd(13): inferred latch for \"RDY\"" {  } { { "PRINTER.vhd" "" { Text "D:/shiy/PRINTER.vhd" 13 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Error" "EVRFX_GENERIC_ERROR_WITH_LOC" "couldn't implement registers for assignments on this clock edge PRINTER.vhd(16) " "Error (10001): Verilog HDL or VHDL error at PRINTER.vhd(16): couldn't implement registers for assignments on this clock edge" {  } { { "PRINTER.vhd" "" { Text "D:/shiy/PRINTER.vhd" 16 0 0 } }  } 0 10001 "Verilog HDL or VHDL error at %2!s!: %1!s!" 0 0}
{ "Error" "EVRFX_GENERIC_ERROR_WITH_LOC" "couldn't implement registers for assignments on this clock edge PRINTER.vhd(17) " "Error (10001): Verilog HDL or VHDL error at PRINTER.vhd(17): couldn't implement registers for assignments on this clock edge" {  } { { "PRINTER.vhd" "" { Text "D:/shiy/PRINTER.vhd" 17 0 0 } }  } 0 10001 "Verilog HDL or VHDL error at %2!s!: %1!s!" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Mar 08 23:37:50 2009 " "Error: Processing ended: Sun Mar 08 23:37:50 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}