edah.hier_info

用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。

|EDAH
clk0 => sysfenpin:u0.clk
y[0] <= corn:u3.q2[0]
y[1] <= corn:u3.q2[1]
y[2] <= corn:u3.q2[2]
y[3] <= corn:u3.q2[3]
y[4] <= corn:u3.q2[4]
y[5] <= corn:u3.q2[5]
y[6] <= corn:u3.q2[6]
y[7] <= corn:u3.q2[7]
q[0] <= docor38a:u4.x[0]
q[1] <= docor38a:u4.x[1]
q[2] <= docor38a:u4.x[2]
q[3] <= docor38a:u4.x[3]
q[4] <= docor38a:u4.x[4]
q[5] <= docor38a:u4.x[5]
q[6] <= docor38a:u4.x[6]
q[7] <= docor38a:u4.x[7]


|EDAH|sysfenpin:u0
clk => cplk~reg0.CLK
clk => tout[0].CLK
clk => tout[1].CLK
clk => tout[2].CLK
clk => tout[3].CLK
clk => tout[4].CLK
clk => tout[5].CLK
clk => tout[6].CLK
clk => tout[7].CLK
clk => tout[8].CLK
clk => tout[9].CLK
clk => tout[10].CLK
keyclk <= keyclk~reg0.DB_MAX_OUTPUT_PORT_TYPE
cplk <= cplk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|EDAH|chw:u1
clk => tmp[0].CLK
clk => tmp[1].CLK
q0[0] <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
q0[1] <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE


|EDAH|saomiao:u2
clk => tmp[0].CLK
clk => tmp[1].CLK
clk => tmp[2].CLK
q1[0] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
q1[1] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
q1[2] <= Add1.DB_MAX_OUTPUT_PORT_TYPE


|EDAH|corn:u3
ch[0] => Mux12.IN5
ch[0] => Mux13.IN5
ch[0] => Mux14.IN5
ch[0] => Mux15.IN5
ch[0] => Mux16.IN5
ch[0] => Mux17.IN5
ch[0] => Mux18.IN5
ch[0] => Mux19.IN5
ch[1] => Mux12.IN4
ch[1] => Mux13.IN4
ch[1] => Mux14.IN4
ch[1] => Mux15.IN4
ch[1] => Mux16.IN4
ch[1] => Mux17.IN4
ch[1] => Mux18.IN4
ch[1] => Mux19.IN4
sel[0] => Mux0.IN10
sel[0] => Mux1.IN5
sel[0] => Mux2.IN10
sel[0] => Mux3.IN5
sel[0] => Mux4.IN10
sel[0] => Mux5.IN10
sel[0] => Mux6.IN10
sel[0] => Mux7.IN10
sel[0] => Mux8.IN10
sel[0] => Mux9.IN10
sel[0] => Mux10.IN10
sel[0] => Mux11.IN10
sel[1] => Mux0.IN9
sel[1] => Mux1.IN4
sel[1] => Mux2.IN9
sel[1] => Mux4.IN9
sel[1] => Mux5.IN9
sel[1] => Mux6.IN9
sel[1] => Mux7.IN9
sel[1] => Mux8.IN9
sel[1] => Mux9.IN9
sel[1] => Mux10.IN9
sel[1] => Mux11.IN9
sel[2] => Mux0.IN8
sel[2] => Mux2.IN8
sel[2] => Mux3.IN4
sel[2] => Mux4.IN8
sel[2] => Mux5.IN8
sel[2] => Mux6.IN8
sel[2] => Mux7.IN8
sel[2] => Mux8.IN8
sel[2] => Mux9.IN8
sel[2] => Mux10.IN8
sel[2] => Mux11.IN8
q2[0] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
q2[1] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
q2[2] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
q2[3] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
q2[4] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
q2[5] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
q2[6] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
q2[7] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE


|EDAH|docor38a:u4
a[0] => Mux0.IN10
a[0] => Mux1.IN10
a[0] => Mux2.IN10
a[0] => Mux3.IN10
a[0] => Mux4.IN10
a[0] => Mux5.IN10
a[0] => Mux6.IN10
a[0] => Mux7.IN10
a[1] => Mux0.IN9
a[1] => Mux1.IN9
a[1] => Mux2.IN9
a[1] => Mux3.IN9
a[1] => Mux4.IN9
a[1] => Mux5.IN9
a[1] => Mux6.IN9
a[1] => Mux7.IN9
a[2] => Mux0.IN8
a[2] => Mux1.IN8
a[2] => Mux2.IN8
a[2] => Mux3.IN8
a[2] => Mux4.IN8
a[2] => Mux5.IN8
a[2] => Mux6.IN8
a[2] => Mux7.IN8
x[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
x[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
x[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
x[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
x[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
x[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
x[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
x[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE