edah.tan.qmsg

用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk0 register sysfenpin:u0\|tout\[4\] register sysfenpin:u0\|tout\[10\] 234.52 MHz 4.264 ns Internal " "Info: Clock \"clk0\" has Internal fmax of 234.52 MHz between source register \"sysfenpin:u0\|tout\[4\]\" and destination register \"sysfenpin:u0\|tout\[10\]\" (period= 4.264 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.993 ns + Longest register register " "Info: + Longest register to register delay is 3.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sysfenpin:u0\|tout\[4\] 1 REG LC_X9_Y6_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y6_N4; Fanout = 4; REG Node = 'sysfenpin:u0\|tout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sysfenpin:u0|tout[4] } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(0.590 ns) 1.709 ns sysfenpin:u0\|Equal0~102 2 COMB LC_X9_Y6_N1 1 " "Info: 2: + IC(1.119 ns) + CELL(0.590 ns) = 1.709 ns; Loc. = LC_X9_Y6_N1; Fanout = 1; COMB Node = 'sysfenpin:u0\|Equal0~102'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.709 ns" { sysfenpin:u0|tout[4] sysfenpin:u0|Equal0~102 } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.114 ns) 2.245 ns sysfenpin:u0\|Equal0~103 3 COMB LC_X9_Y6_N3 6 " "Info: 3: + IC(0.422 ns) + CELL(0.114 ns) = 2.245 ns; Loc. = LC_X9_Y6_N3; Fanout = 6; COMB Node = 'sysfenpin:u0\|Equal0~103'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.536 ns" { sysfenpin:u0|Equal0~102 sysfenpin:u0|Equal0~103 } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.270 ns) + CELL(0.478 ns) 3.993 ns sysfenpin:u0\|tout\[10\] 4 REG LC_X9_Y5_N6 3 " "Info: 4: + IC(1.270 ns) + CELL(0.478 ns) = 3.993 ns; Loc. = LC_X9_Y5_N6; Fanout = 3; REG Node = 'sysfenpin:u0\|tout\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.748 ns" { sysfenpin:u0|Equal0~103 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.182 ns ( 29.60 % ) " "Info: Total cell delay = 1.182 ns ( 29.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.811 ns ( 70.40 % ) " "Info: Total interconnect delay = 2.811 ns ( 70.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.993 ns" { sysfenpin:u0|tout[4] sysfenpin:u0|Equal0~102 sysfenpin:u0|Equal0~103 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.993 ns" { sysfenpin:u0|tout[4] sysfenpin:u0|Equal0~102 sysfenpin:u0|Equal0~103 sysfenpin:u0|tout[10] } { 0.000ns 1.119ns 0.422ns 1.270ns } { 0.000ns 0.590ns 0.114ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.010 ns - Smallest " "Info: - Smallest clock skew is -0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk0\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_17 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 12; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "EDAH.vhd" "" { Text "F:/liudehua/EDAH/EDAH.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns sysfenpin:u0\|tout\[10\] 2 REG LC_X9_Y5_N6 3 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N6; Fanout = 3; REG Node = 'sysfenpin:u0\|tout\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.261 ns" { clk0 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk0 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.730 ns" { clk0 clk0~out0 sysfenpin:u0|tout[10] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.740 ns - Longest register " "Info: - Longest clock path from clock \"clk0\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_17 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 12; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "EDAH.vhd" "" { Text "F:/liudehua/EDAH/EDAH.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns sysfenpin:u0\|tout\[4\] 2 REG LC_X9_Y6_N4 4 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X9_Y6_N4; Fanout = 4; REG Node = 'sysfenpin:u0\|tout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { clk0 sysfenpin:u0|tout[4] } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk0 sysfenpin:u0|tout[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk0 clk0~out0 sysfenpin:u0|tout[4] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk0 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.730 ns" { clk0 clk0~out0 sysfenpin:u0|tout[10] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk0 sysfenpin:u0|tout[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk0 clk0~out0 sysfenpin:u0|tout[4] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.993 ns" { sysfenpin:u0|tout[4] sysfenpin:u0|Equal0~102 sysfenpin:u0|Equal0~103 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.993 ns" { sysfenpin:u0|tout[4] sysfenpin:u0|Equal0~102 sysfenpin:u0|Equal0~103 sysfenpin:u0|tout[10] } { 0.000ns 1.119ns 0.422ns 1.270ns } { 0.000ns 0.590ns 0.114ns 0.478ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.730 ns" { clk0 sysfenpin:u0|tout[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.730 ns" { clk0 clk0~out0 sysfenpin:u0|tout[10] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk0 sysfenpin:u0|tout[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk0 clk0~out0 sysfenpin:u0|tout[4] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk0 y\[0\] chw:u1\|tmp\[1\] 21.005 ns register " "Info: tco from clock \"clk0\" to destination pin \"y\[0\]\" through register \"chw:u1\|tmp\[1\]\" is 21.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 12.463 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to source register is 12.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_17 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 12; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "EDAH.vhd" "" { Text "F:/liudehua/EDAH/EDAH.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns sysfenpin:u0\|cplk 2 REG LC_X8_Y6_N2 12 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 12; REG Node = 'sysfenpin:u0\|cplk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.495 ns" { clk0 sysfenpin:u0|cplk } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.484 ns) + CELL(0.935 ns) 7.383 ns sysfenpin:u0\|keyclk 3 REG LC_X12_Y9_N4 2 " "Info: 3: + IC(3.484 ns) + CELL(0.935 ns) = 7.383 ns; Loc. = LC_X12_Y9_N4; Fanout = 2; REG Node = 'sysfenpin:u0\|keyclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.419 ns" { sysfenpin:u0|cplk sysfenpin:u0|keyclk } "NODE_NAME" } } { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.369 ns) + CELL(0.711 ns) 12.463 ns chw:u1\|tmp\[1\] 4 REG LC_X12_Y10_N5 12 " "Info: 4: + IC(4.369 ns) + CELL(0.711 ns) = 12.463 ns; Loc. = LC_X12_Y10_N5; Fanout = 12; REG Node = 'chw:u1\|tmp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.080 ns" { sysfenpin:u0|keyclk chw:u1|tmp[1] } "NODE_NAME" } } { "../chw/chw.vhd" "" { Text "F:/liudehua/chw/chw.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.50 % ) " "Info: Total cell delay = 4.050 ns ( 32.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.413 ns ( 67.50 % ) " "Info: Total interconnect delay = 8.413 ns ( 67.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.463 ns" { clk0 sysfenpin:u0|cplk sysfenpin:u0|keyclk chw:u1|tmp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.463 ns" { clk0 clk0~out0 sysfenpin:u0|cplk sysfenpin:u0|keyclk chw:u1|tmp[1] } { 0.000ns 0.000ns 0.560ns 3.484ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../chw/chw.vhd" "" { Text "F:/liudehua/chw/chw.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.318 ns + Longest register pin " "Info: + Longest register to pin delay is 8.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns chw:u1\|tmp\[1\] 1 REG LC_X12_Y10_N5 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N5; Fanout = 12; REG Node = 'chw:u1\|tmp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { chw:u1|tmp[1] } "NODE_NAME" } } { "../chw/chw.vhd" "" { Text "F:/liudehua/chw/chw.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.680 ns) + CELL(0.442 ns) 2.122 ns corn:u3\|Mux19~342 2 COMB LC_X10_Y8_N1 2 " "Info: 2: + IC(1.680 ns) + CELL(0.442 ns) = 2.122 ns; Loc. = LC_X10_Y8_N1; Fanout = 2; COMB Node = 'corn:u3\|Mux19~342'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.122 ns" { chw:u1|tmp[1] corn:u3|Mux19~342 } "NODE_NAME" } } { "../corn/corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.590 ns) 4.003 ns corn:u3\|Mux19~343 3 COMB LC_X10_Y10_N9 1 " "Info: 3: + IC(1.291 ns) + CELL(0.590 ns) = 4.003 ns; Loc. = LC_X10_Y10_N9; Fanout = 1; COMB Node = 'corn:u3\|Mux19~343'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.881 ns" { corn:u3|Mux19~342 corn:u3|Mux19~343 } "NODE_NAME" } } { "../corn/corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.207 ns) + CELL(2.108 ns) 8.318 ns y\[0\] 4 PIN PIN_50 0 " "Info: 4: + IC(2.207 ns) + CELL(2.108 ns) = 8.318 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'y\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.315 ns" { corn:u3|Mux19~343 y[0] } "NODE_NAME" } } { "EDAH.vhd" "" { Text "F:/liudehua/EDAH/EDAH.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.140 ns ( 37.75 % ) " "Info: Total cell delay = 3.140 ns ( 37.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.178 ns ( 62.25 % ) " "Info: Total interconnect delay = 5.178 ns ( 62.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.318 ns" { chw:u1|tmp[1] corn:u3|Mux19~342 corn:u3|Mux19~343 y[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.318 ns" { chw:u1|tmp[1] corn:u3|Mux19~342 corn:u3|Mux19~343 y[0] } { 0.000ns 1.680ns 1.291ns 2.207ns } { 0.000ns 0.442ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.463 ns" { clk0 sysfenpin:u0|cplk sysfenpin:u0|keyclk chw:u1|tmp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.463 ns" { clk0 clk0~out0 sysfenpin:u0|cplk sysfenpin:u0|keyclk chw:u1|tmp[1] } { 0.000ns 0.000ns 0.560ns 3.484ns 4.369ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.318 ns" { chw:u1|tmp[1] corn:u3|Mux19~342 corn:u3|Mux19~343 y[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.318 ns" { chw:u1|tmp[1] corn:u3|Mux19~342 corn:u3|Mux19~343 y[0] } { 0.000ns 1.680ns 1.291ns 2.207ns } { 0.000ns 0.442ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 01 10:30:00 2008 " "Info: Processing ended: Mon Dec 01 10:30:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}