nandflash.tlg

来自「用VHDL开发的NANDFLASH的读写程序,给出 NANDFLASH的时序正」· TLG 代码 · 共 31 行

@N: CD630 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":21:7:21:20|Synthesizing work.test_nandflash.translated 
Post processing for work.test_nandflash.translated
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT(6) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT(5) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT(3) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT(2) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT(1) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT(0) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Register bit repeat_addr_maxCNT(0) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Register bit repeat_addr_maxCNT(1) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Register bit repeat_addr_maxCNT(2) is always 0, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Register bit repeat_rdata_maxCNT(0) is always 1, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Register bit repeat_rdata_maxCNT(1) is always 1, optimizing ...
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Register bit repeat_rdata_maxCNT(2) is always 0, optimizing ...
@N: CL177 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Sharing sequential element LoadRPcnt_rdata.
@W: CL189 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":195:6:195:7|Register bit NFL_DATA_OUT_cl(7) is always 1, optimizing ...
@N: CL201 :"D:\Synplicity\NANDFLASH\NANDFLASH.vhd":233:6:233:7|Trying to extract state machine for register OP_STATE
Extracted state machine for register OP_STATE
State machine has 11 reachable states with original encodings of:
   00000000
   00000001
   00000010
   00000011
   00000100
   00000101
   00000110
   00000111
   00001000
   00001001
   00001010