📄 de2_tv.v
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//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
input TD_CLK; // TV Decoder Line Locked Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
////////////////////////////////////////////////////////////////////
// Enable TV Decoder
assign TD_RESET = KEY[0];
// For Audio CODEC
wire AUD_CTRL_CLK; // For Audio Controller
assign AUD_XCK = AUD_CTRL_CLK;
assign LED_GREEN = VGA_Y;
assign LED_RED = VGA_X;
// 7 segment LUT
SEG7_LUT_8 u0 ( .oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.oSEG6(HEX6),
.oSEG7(HEX7),
.iDIG(DPDT_SW) );
// Audio CODEC and video decoder setting
I2C_AV_Config u1 ( // Host Side
.iCLK(OSC_50),
.iRST_N(KEY[0]),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
// TV Decoder Stable Check
TD_Detect u2 ( .oTD_Stable(TD_Stable),
.iTD_VS(TD_VS),
.iTD_HS(TD_HS),
.iRST_N(KEY[0]) );
// Reset Delay Timer
Reset_Delay u3 ( .iCLK(OSC_50),
.iRST(TD_Stable),
.oRST_0(DLY0),
.oRST_1(DLY1),
.oRST_2(DLY2));
// ITU-R 656 to YUV 4:2:2
ITU_656_Decoder u4 ( // TV Decoder Input
.iTD_DATA(TD_DATA),
// Position Output
.oTV_X(TV_X),
// YUV 4:2:2 Output
.oYCbCr(YCbCr),
.oDVAL(TV_DVAL),
// Control Signals
.iSwap_CbCr(Quotient[0]),
.iSkip(Remain==4'h0),
.iRST_N(DLY1),
.iCLK_27(TD_CLK) );
// For Down Sample 720 to 640
DIV u5 ( .aclr(!DLY0),
.clock(TD_CLK),
.denom(4'h9),
.numer(TV_X),
.quotient(Quotient),
.remain(Remain));
// SDRAM frame buffer
Sdram_Control_4Port u6 ( // HOST Side
.REF_CLK(OSC_27),
.CLK_18(AUD_CTRL_CLK),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA(YCbCr),
.WR1(TV_DVAL),
.WR1_FULL(WR1_FULL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*507), // 525-18
.WR1_LENGTH(9'h80),
.WR1_LOAD(!DLY0),
.WR1_CLK(TD_CLK),
// FIFO Read Side 1
.RD1_DATA(m1YCbCr),
.RD1(m1VGA_Read),
.RD1_ADDR(640*13), // Read odd field and bypess blanking
.RD1_MAX_ADDR(640*253),
.RD1_LENGTH(9'h80),
.RD1_LOAD(!DLY0),
.RD1_CLK(OSC_27),
// FIFO Read Side 2
.RD2_DATA(m2YCbCr),
.RD2(m2VGA_Read),
.RD2_ADDR(640*267), // Read even field and bypess blanking
.RD2_MAX_ADDR(640*507),
.RD2_LENGTH(9'h80),
.RD2_LOAD(!DLY0),
.RD2_CLK(OSC_27),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
// YUV 4:2:2 to YUV 4:4:4
YUV422_to_444 u7 ( // YUV 4:2:2 Input
.iYCbCr(mYCbCr),
// YUV 4:4:4 Output
.oY(mY),
.oCb(mCb),
.oCr(mCr),
// Control Signals
.iX(VGA_X),
.iCLK(OSC_27),
.iRST_N(DLY0));
// YCbCr 8-bit to RGB-10 bit
YCbCr2RGB u8 ( // Output Side
.Red(mRed),
.Green(mGreen),
.Blue(mBlue),
.oDVAL(mDVAL),
// Input Side
.iY(mY),
.iCb(mCb),
.iCr(mCr),
.iDVAL(VGA_Read),
// Control Signal
.iRESET(!DLY2),
.iCLK(OSC_27));
// VGA Controller
VGA_Ctrl u9 ( // Host Side
.iRed(mRed),
.iGreen(mGreen),
.iBlue(mBlue),
.oCurrent_X(VGA_X),
.oCurrent_Y(VGA_Y),
.oRequest(VGA_Read),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
.oVGA_CLOCK(VGA_CLK),
// Control Signal
.iCLK(OSC_27),
.iRST_N(DLY2) );
// For ITU-R 656 Decoder
wire [15:0] YCbCr;
wire [9:0] TV_X;
wire TV_DVAL;
// For VGA Controller
wire [9:0] mRed;
wire [9:0] mGreen;
wire [9:0] mBlue;
wire [10:0] VGA_X;
wire [10:0] VGA_Y;
wire VGA_Read; // VGA data request
wire m1VGA_Read; // Read odd field
wire m2VGA_Read; // Read even field
// For YUV 4:2:2 to YUV 4:4:4
wire [7:0] mY;
wire [7:0] mCb;
wire [7:0] mCr;
// For field select
wire [15:0] mYCbCr;
wire [15:0] mYCbCr_d;
wire [15:0] m1YCbCr;
wire [15:0] m2YCbCr;
wire [15:0] m3YCbCr;
// For Delay Timer
wire TD_Stable;
wire DLY0;
wire DLY1;
wire DLY2;
// For Down Sample
wire [3:0] Remain;
wire [9:0] Quotient;
assign m1VGA_Read = VGA_Y[0] ? 1'b0 : VGA_Read ;
assign m2VGA_Read = VGA_Y[0] ? VGA_Read : 1'b0 ;
assign mYCbCr_d = !VGA_Y[0] ? m1YCbCr :
m2YCbCr ;
assign mYCbCr = m5YCbCr;
wire mDVAL;
// Line buffer, delay one line
Line_Buffer u10 ( .clken(VGA_Read),
.clock(OSC_27),
.shiftin(mYCbCr_d),
.shiftout(m3YCbCr));
Line_Buffer u11 ( .clken(VGA_Read),
.clock(OSC_27),
.shiftin(m3YCbCr),
.shiftout(m4YCbCr));
wire [15:0] m4YCbCr;
wire [15:0] m5YCbCr;
wire [8:0] Tmp1,Tmp2;
wire [7:0] Tmp3,Tmp4;
assign Tmp1 = m4YCbCr[7:0]+mYCbCr_d[7:0];
assign Tmp2 = m4YCbCr[15:8]+mYCbCr_d[15:8];
assign Tmp3 = Tmp1[8:2]+m3YCbCr[7:1];
assign Tmp4 = Tmp2[8:2]+m3YCbCr[15:9];
assign m5YCbCr = {Tmp4,Tmp3};
AUDIO_DAC u12 ( // Audio Side
.oAUD_BCK(AUD_BCLK),
.oAUD_DATA(AUD_DACDAT),
.oAUD_LRCK(AUD_DACLRCK),
// Control Signals
.iSrc_Select(2'b01),
.iCLK_18_4(AUD_CTRL_CLK),
.iRST_N(DLY1) );
endmodule⌨️ 快捷键说明
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