dff.vhd

来自「This is a project about PWM. Application」· VHDL 代码 · 共 28 行

----------------------------------------------------------------------------
-- d-flipflop 
----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
  port(
    clk: in std_logic;
    input: in std_logic;
    output: out std_logic
  );
end dff;

architecture behavioral of dff is
begin
  process(clk)
    begin
      if rising_edge(clk) then
	output <= input;
      end if;
    end process;
end behavioral;