toplevel.par

This is a project about PWM. Application in motor speed control

Release 8.1i par I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

dutigm.st.ewi.tudelft.nl::  Fri Jul 14 21:31:59 2006

par -w -intstyle xflow -ol std -t 1 toplevel_map.ncd toplevel.ncd toplevel.pcf 


Constraints file: toplevel.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment /root/Xilinx.
   "toplevel" is an NCD, version 3.1, device xc3s400, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.37 2005-11-04".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            28 out of 173    16%
      Number of LOCed IOBs            28 out of 28    100%

   Number of Slices                  502 out of 3584   14%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

WARNING:Par:276 - The signal button<2>_IBUF has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989f57) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 7 secs 

Phase 4.8
...........................................
..
..................................................
..
..
............
Phase 4.8 (Checksum:a618af) REAL time: 14 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 14 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 18 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 18 secs 

Writing design to file toplevel.ncd


Total REAL time to Placer completion: 18 secs 
Total CPU time to Placer completion: 17 secs 

Starting Router

Phase 1: 2969 unrouted;       REAL time: 18 secs 

Phase 2: 2674 unrouted;       REAL time: 19 secs 

Phase 3: 1088 unrouted;       REAL time: 19 secs 

Phase 4: 1088 unrouted; (32192)      REAL time: 19 secs 

Phase 5: 1084 unrouted; (0)      REAL time: 20 secs 

Phase 6: 0 unrouted; (0)      REAL time: 21 secs 

Phase 7: 0 unrouted; (0)      REAL time: 22 secs 


Total REAL time to Router completion: 22 secs 
Total CPU time to Router completion: 21 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|     clk_50Mhz_BUFGP |      BUFGMUX0| No   |  269 |  0.060     |  1.074      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.955
   The MAXIMUM PIN DELAY IS:                               5.367
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   4.247

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1619        1141         126          43          13           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of  
                                            |            |            | Levels | Slack      |errors     
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 9.062ns    | 18     | N/A        | N/A       
  _50Mhz_BUFGP                              |            |            |        |            |           
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

WARNING:Par:284 - There are 1 sourceless or loadless signals in this design.

Total REAL time to PAR completion: 23 secs 
Total CPU time to PAR completion: 22 secs 

Peak Memory Usage:  123 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file toplevel.ncd



PAR done!