xilinx.mf

This is a project about PWM. Application in motor speed control

###############################################################################
##                                                                           ##
##                        project-dependent variables                        ##
##                                                                           ##
###############################################################################

# The project name. The bit-file that is generated in the end will be named
# "$(PROJ).bit"

#PROJ = demo

# The top-level entity to be instantiated

#TOPLEVEL = demo

# Short board identification.
# Currently supported: "memec", "nuhorizons", "xilinx"

# The VHDL sources that need to be compiled during synthesis

#VHDL_SOURCES = demo.vhdl hexnibble.vhdl

# The default target; recommended targets: "bitfile" or "upload"

#default : bitfile

# A directory for temporary files (must exist)
# WIN32 CHANGE: USED TO BE /tmp
TMPDIR=tmp


###############################################################################
##                                                                           ##
##            miscellaneous project-independent variables & rules            ##
##                                                                           ##
###############################################################################

# Setup directories and files

FPGA_TYPE       = xc3s400-ft256-4
JTAG_INDEX_FPGA = 0
JTAG_INDEX_PROM = 1

# use this to make most tools quieter
#OPT_INTSTYLE = -intstyle ise
OPT_INTSTYLE = -intstyle xflow

# Phony (non file creating) targets

.PHONY : default clean bitfile upload upload-prom

xilinxclean :
	# WIN32 CHANGE: commented next line, generates errors
	#$(RM) -rf *~ work dump.xst _ngo
	$(RM) $(PROJ).xst-script
	$(RM) $(PROJ).lso $(PROJ).prj
	$(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
	$(RM) $(PROJ).ngd $(PROJ).bld
	$(RM) $(PROJ).twx $(PROJ).twr
	$(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm
	$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
	$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
	$(RM) $(PROJ).unroutes

bitfile : $(PROJ).bit

upload : $(PROJ).bit
	xc3sprog $< $(JTAG_INDEX_FPGA)

upload-prom : $(PROJ).bit
	xc3sprog $< $(JTAG_INDEX_PROM)

###############################################################################
#                                                                             #
#                    STAGE 1: "xst" (Xilinx Synthesis Tool)                   #
#  needs:                                                                     #
#                                                                             #
#    $(PROJ).vhdl                                                             #
#    $(PROJ).prj - Project file (created below)                               #
#    $(PROJ).lso - Library Search Order file (created below)                  #
#                                                                             #
#  created files:                                                             #
#                                                                             #
#    $(PROJ).ngc     - netlist                                                #
#    $(PROJ).ngr     - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e       #
#                      (optional, depending on the '-rtlview' option)         #
#    $(PROJ).xst.log - human-readable synthesis report                        #
#                      (AKA .syr, .srp)                                       #
#                                                                             #
#  created directories:                                                       #
#                                                                             #
#    work                                                                     #
#    dump.xst                                                                 #
#                                                                             #
###############################################################################

# Generate a "Library Search Order" file, containing just "work" for now.

$(PROJ).lso :
	@echo "work" > $@

# Generate a "Project" file, consisting of lines containing each of the
# VHDL_SOURCES, preceded by "vhdl work".

$(PROJ).prj :
# WIN32 CHANGE: Used to be:
    ifndef WIN32
	$(shell echo -n $(VHDL_SOURCES) | \
	sed 's/\([^ ]\+\) */vhdl work \1\n/g' > $@)
    endif
    ifdef WIN32
	@echo $(foreach SOURCE,$(VHDL_SOURCES),vhdl work $(SOURCE)\\n) >>$@
    endif

$(PROJ).xst-script :
	@echo "set -tmpdir $(TMPDIR)"                                   > $@
	@echo "set -xsthdpdir ."                                       >> $@
	@echo "run"                                                    >> $@
	@echo "-ifn                                  $(PROJ).prj"      >> $@
	@echo "-ifmt                                 mixed"            >> $@
	@echo "-ofn                                  $(PROJ)"          >> $@
	@echo "-ofmt                                 ngc"              >> $@
	@echo "-p                                    $(FPGA_TYPE)"     >> $@
	@echo "-top                                  $(TOPLEVEL)"      >> $@
	@echo "-opt_mode                             speed"            >> $@
	@echo "-opt_level                            1"                >> $@
	@echo "-iuc                                  no"               >> $@
	@echo "-lso                                  $(PROJ).lso"      >> $@
	@echo "-keep_hierarchy                       no"               >> $@
	@echo "-glob_opt                             AllClockNets"     >> $@
	@echo "-rtlview                              no"               >> $@
	@echo "-read_cores                           yes"              >> $@
	@echo "-write_timing_constraints             no"               >> $@
	@echo "-cross_clock_analysis                 no"               >> $@
	@echo "-hierarchy_separator                  _"                >> $@
	@echo "-bus_delimiter                        <>"               >> $@
	@echo "-case                                 maintain"         >> $@
	@echo "-slice_utilization_ratio              100"              >> $@
	@echo "-verilog2001                          yes"              >> $@
	@echo "-vlgincdir"                                             >> $@
	@echo "-fsm_extract                          yes"              >> $@
	@echo "-fsm_encoding                         auto"             >> $@
	@echo "-fsm_style                            lut"              >> $@
	@echo "-ram_extract                          yes"              >> $@
	@echo "-ram_style                            auto"             >> $@
	@echo "-rom_extract                          yes"              >> $@
	@echo "-rom_style                            auto"             >> $@
	@echo "-mux_extract                          yes"              >> $@
	@echo "-mux_style                            auto"             >> $@
	@echo "-decoder_extract                      yes"              >> $@