toplevel.xst.log

This is a project about PWM. Application in motor speed control

WARNING:Xst:1291 - FF/Latch <counter1_count_30> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_31> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_16> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_17> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_18> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_19> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_20> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_21> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_22> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_23> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_24> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_25> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_26> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_27> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_28> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_29> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_30> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_c_31> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_7> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_16> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_17> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_18> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_19> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_20> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_21> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_22> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_23> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_24> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_25> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_26> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_27> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_28> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_29> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_30> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter0_count_31> is unconnected in block <toplevel>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block toplevel, actual ratio is 13.
FlipFlop autorepeat0_state_FFd1 has been replicated 4 time(s)
FlipFlop autorepeat0_state_FFd2 has been replicated 5 time(s)
FlipFlop autorepeat1_state_FFd1 has been replicated 4 time(s)
FlipFlop autorepeat1_state_FFd2 has been replicated 5 time(s)
FlipFlop decoder0_dn has been replicated 1 time(s)
FlipFlop dpc0_pulse has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : toplevel
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 28

Cell Usage :
# BELS                             : 1769
#      GND                         : 1
#      INV                         : 170
#      LUT1                        : 37
#      LUT1_L                      : 188
#      LUT2                        : 11
#      LUT2_L                      : 38
#      LUT3                        : 14
#      LUT3_D                      : 20
#      LUT3_L                      : 70
#      LUT4                        : 47
#      LUT4_D                      : 23
#      LUT4_L                      : 308
#      MUXCY                       : 528
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 305
# FlipFlops/Latches                : 414
#      FD                          : 337
#      FDE                         : 1
#      FDR                         : 70
#      FDS                         : 6
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 26
#      IBUF                        : 5
#      OBUF                        : 21
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of Slices:                     506  out of   3584    14%  
 Number of Slice Flip Flops:           410  out of   7168     5%  
 Number of 4 input LUTs:               756  out of   7168    10%  
 Number of bonded IOBs:                 28  out of    173    16%  
    IOB Flip Flops: 4
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_50Mhz                          | BUFGP                  | 414   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.620ns (Maximum Frequency: 116.009MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.709ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_50Mhz'
  Clock period: 8.620ns (frequency: 116.009MHz)
  Total number of paths / destination ports: 35459 / 481
-------------------------------------------------------------------------
Delay:               8.620ns (Levels of Logic = 35)
  Source:            debouncer5_count_0 (FF)
  Destination:       debouncer5_count_9 (FF)
  Source Clock:      clk_50Mhz rising
  Destination Clock: clk_50Mhz rising

  Data Path: debouncer5_count_0 to debouncer5_count_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.720   0.917  debouncer5_count_0 (debouncer5_count_0)
     INV:I->O              1   0.551   0.000  debouncer5_Mcompar__n0000_xnorlut8_INV_0 (debouncer5_N4)
     MUXCY:S->O            1   0.500   0.000  debouncer5_Mcompar__n0000_xnorcy (debouncer5_Mcompar__n0000_xnor_cyo)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_0 (debouncer5_Mcompar__n0000_xnor_cyo1)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_1 (debouncer5_Mcompar__n0000_xnor_cyo2)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_2 (debouncer5_Mcompar__n0000_xnor_cyo3)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_3 (debouncer5_Mcompar__n0000_xnor_cyo4)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_4 (debouncer5_Mcompar__n0000_xnor_cyo5)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_5 (debouncer5_Mcompar__n0000_xnor_cyo6)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_6 (debouncer5_Mcompar__n0000_xnor_cyo7)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_7 (debouncer5_Mcompar__n0000_xnor_cyo8)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_8 (debouncer5_Mcompar__n0000_xnor_cyo9)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_9 (debouncer5_Mcompar__n0000_xnor_cyo10)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_10 (debouncer5_Mcompar__n0000_xnor_cyo11)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_11 (debouncer5_Mcompar__n0000_xnor_cyo12)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_12 (debouncer5_Mcompar__n0000_xnor_cyo13)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_13 (debouncer5_Mcompar__n0000_xnor_cyo14)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_14 (debouncer5_Mcompar__n0000_xnor_cyo15)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_15 (debouncer5_Mcompar__n0000_xnor_cyo16)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_16 (debouncer5_Mcompar__n0000_xnor_cyo17)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_17 (debouncer5_Mcompar__n0000_xnor_cyo18)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_18 (debouncer5_Mcompar__n0000_xnor_cyo19)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_19 (debouncer5_Mcompar__n0000_xnor_cyo20)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_20 (debouncer5_Mcompar__n0000_xnor_cyo21)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_21 (debouncer5_Mcompar__n0000_xnor_cyo22)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_22 (debouncer5_Mcompar__n0000_xnor_cyo23)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_23 (debouncer5_Mcompar__n0000_xnor_cyo24)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_24 (debouncer5_Mcompar__n0000_xnor_cyo25)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_25 (debouncer5_Mcompar__n0000_xnor_cyo26)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_26 (debouncer5_Mcompar__n0000_xnor_cyo27)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_27 (debouncer5_Mcompar__n0000_xnor_cyo28)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_28 (debouncer5_Mcompar__n0000_xnor_cyo29)
     MUXCY:CI->O           1   0.064   0.000  debouncer5_Mcompar__n0000_xnorcy_rn_29 (debouncer5_Mcompar__n0000_xnor_cyo30)
     MUXCY:CI->O          11   0.303   1.212  debouncer5_Mcompar__n0000_xnorcy_rn_30 (debouncer5_Mcompar__n0000_xnor_cyo31)
     LUT3_D:I2->O          9   0.551   1.192  debouncer5_Ker21_3 (debouncer5_Ker212)
     LUT4_L:I2->LO         1   0.551   0.000  debouncer5__n0004<17>1 (debouncer5__n0004<17>)
     FD:D                      0.203          debouncer5_count_17
    ----------------------------------------
    Total                      8.620ns (5.299ns logic, 3.321ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_50Mhz'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            io_b1_09 (PAD)
  Destination:       dff5_output (FF)
  Destination Clock: clk_50Mhz rising

  Data Path: io_b1_09 to dff5_output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  io_b1_09_IBUF (io_b1_09_IBUF)
     FD:D                      0.203          dff5_output
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_50Mhz'
  Total number of paths / destination ports: 19 / 19
-------------------------------------------------------------------------
Offset:              7.709ns (Levels of Logic = 1)
  Source:            decoder0_dn (FF)
  Destination:       led<5> (PAD)
  Source Clock:      clk_50Mhz rising

  Data Path: decoder0_dn to led<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q             17   0.720   1.345  decoder0_dn (decoder0_dn)
     OBUF:I->O                 5.644          led_5_OBUF (led<5>)
    ----------------------------------------
    Total                      7.709ns (6.364ns logic, 1.345ns route)
                                       (82.6% logic, 17.4% route)

=========================================================================
CPU : 18.45 / 18.55 s | Elapsed : 21.00 / 22.00 s
 
--> 


Total memory usage is 97736 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   95 (   0 filtered)
Number of infos    :    1 (   0 filtered)