toplevel.xst.log

This is a project about PWM. Application in motor speed control

    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <count>.
    Found 32-bit addsub for signal <$n0004> created at line 41.
    Found 32-bit register for signal <c>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  64 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <counter> synthesized.


Synthesizing Unit <decoder>.
    Related source file is "/root/FPGA/Cruise/decoder.vhd".
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 25                                             |
    | Inputs             | 3                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Power Up State     | init                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <dn>.
    Found 1-bit register for signal <up>.
    Found 1-bit register for signal <trigger>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 D-type flip-flop(s).
Unit <decoder> synthesized.


Synthesizing Unit <debouncer>.
    Related source file is "/root/FPGA/Cruise/debouncer.vhd".
    Found finite state machine <FSM_3> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Power Up State     | standby                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <debounced>.
    Found 32-bit comparator less for signal <$n0000> created at line 39.
    Found 32-bit adder for signal <$n0006> created at line 29.
    Found 32-bit register for signal <count>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <debouncer> synthesized.


Synthesizing Unit <dff>.
    Related source file is "/root/FPGA/Cruise/dff.vhd".
    Found 1-bit register for signal <output>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <dff> synthesized.


Synthesizing Unit <toplevel>.
    Related source file is "/root/FPGA/Cruise/toplevel.vhd".
WARNING:Xst:646 - Signal <count<31:16>> is assigned but never used.
WARNING:Xst:646 - Signal <count<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <debounced_button<2>> is assigned but never used.
WARNING:Xst:646 - Signal <speed<31:8>> is assigned but never used.
Unit <toplevel> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 2
 16x7-bit ROM                                          : 1
 4x4-bit ROM                                           : 1
# Adders/Subtractors                                   : 10
 32-bit adder                                          : 6
 32-bit addsub                                         : 4
# Counters                                             : 3
 11-bit up counter                                     : 1
 32-bit up counter                                     : 2
# Registers                                            : 45
 1-bit register                                        : 32
 32-bit register                                       : 12
 4-bit register                                        : 1
# Comparators                                          : 10
 32-bit comparator greatequal                          : 2
 32-bit comparator greater                             : 2
 32-bit comparator less                                : 6
# Multiplexers                                         : 1
 4-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <debouncer0/state> on signal <state[1:2]> with gray encoding.
----------------------
 State    | Encoding
----------------------
 standby  | 00
 pressed  | 01
 released | 11
----------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <decoder0/state> on signal <state[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 init  | 000
 s00   | 100
 s01   | 011
 s10   | 010
 s11   | 001
 error | 101
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <counter0/s> on signal <s[1:2]> with sequential encoding.
---------------------
 State   | Encoding
---------------------
 standby | 00
 up      | 10
 dn      | 01
---------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <autorepeat0/state> on signal <state[1:2]> with gray encoding.
--------------------
 State  | Encoding
--------------------
 stdby  | 00
 press0 | 01
 press1 | 11
 press2 | 10
--------------------
WARNING:Xst:524 - All outputs of the instance <dff2> of the block <dff> are unconnected in block <toplevel>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <debouncer2> of the block <debouncer> are unconnected in block <toplevel>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 4
# ROMs                                                 : 2
 16x7-bit ROM                                          : 1
 4x4-bit ROM                                           : 1
# Adders/Subtractors                                   : 9
 32-bit adder                                          : 5
 32-bit addsub                                         : 4
# Counters                                             : 3
 11-bit up counter                                     : 1
 32-bit up counter                                     : 2
# Registers                                            : 162
 Flip-Flops                                            : 162
# Comparators                                          : 9
 32-bit comparator greatequal                          : 2
 32-bit comparator greater                             : 2
 32-bit comparator less                                : 5
# Multiplexers                                         : 1
 4-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch ssd_7 hinder the constant cleaning in the block hex2ssd.
   You should achieve better results by setting this init to 1.
Loading device for application Rf_Device from file '3s400.nph' in environment /root/Xilinx.

Optimizing unit <toplevel> ...

Optimizing unit <hex2ssd> ...

Optimizing unit <debouncer> ...

Optimizing unit <counter> ...

Optimizing unit <autorepeat> ...

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <counter1_c_8> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_9> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_10> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_11> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_12> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_13> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_14> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_15> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_16> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_17> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_18> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_19> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_20> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_21> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_22> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_23> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_24> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_25> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_26> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_27> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_28> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_29> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_30> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_c_31> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_8> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_9> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_10> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_11> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_12> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_13> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_14> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_15> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_16> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_17> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_18> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_19> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_20> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_21> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_22> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_23> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_24> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_25> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_26> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_27> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_28> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <counter1_count_29> is unconnected in block <toplevel>.