toplevel.xst.log

This is a project about PWM. Application in motor speed control

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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Reading design: toplevel.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "toplevel.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : no
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : "toplevel"
Output Format                      : ngc
Target Device                      : xc3s400-ft256-4

---- Source Options
Top Module Name                    : toplevel
Automatic FSM Extraction           : yes
FSM Encoding Algorithm             : auto
FSM Style                          : lut
RAM Extraction                     : yes
RAM Style                          : auto
ROM Extraction                     : yes
ROM Style                          : auto
Mux Extraction                     : yes
Mux Style                          : auto
Decoder Extraction                 : yes
Priority Encoder Extraction        : yes
Shift Register Extraction          : yes
Logical Shifter Extraction         : yes
XOR Collapsing                     : yes
Resource Sharing                   : yes
Multiplier Style                   : auto
Automatic Register Balancing       : no

---- Target Options
Add IO Buffers                     : yes
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : yes
Equivalent register Removal        : yes
Slice Packing                      : yes
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Keep Hierarchy                     : no
Global Optimization                : AllClockNets
RTL Output                         : no
Write Timing Constraints           : no
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100

---- Other Options
lso                                : toplevel.lso
Read Cores                         : yes
cross_clock_analysis               : no
verilog2001                        : yes
Optimize Instantiated Primitives   : no

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/root/FPGA/Cruise/oneshot.vhd" in Library work.
Entity <oneshot> compiled.
Entity <oneshot> (Architecture <behavior>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/dff.vhd" in Library work.
Entity <dff> compiled.
Entity <dff> (Architecture <behavioral>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/debouncer.vhd" in Library work.
Entity <debouncer> compiled.
Entity <debouncer> (Architecture <behavior>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/decoder.vhd" in Library work.
Entity <decoder> compiled.
Entity <decoder> (Architecture <behavior>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/counter.vhd" in Library work.
Entity <counter> compiled.
Entity <counter> (Architecture <behavior>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/autorepeat.vhd" in Library work.
Entity <autorepeat> compiled.
Entity <autorepeat> (Architecture <behaviour>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/dpc.vhd" in Library work.
Entity <dpc> compiled.
Entity <dpc> (Architecture <behaviour>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/hex2ssd.vhd" in Library work.
Entity <hex2ssd> compiled.
Entity <hex2ssd> (Architecture <behavioral>) compiled.
Compiling vhdl file "/root/FPGA/Cruise/toplevel.vhd" in Library work.
Entity <toplevel> compiled.
Entity <toplevel> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <toplevel> (Architecture <behavioral>).
    Set user-defined property "LOC =  T9" for signal <clk_50Mhz> in unit <toplevel>.
    Set user-defined property "LOC =  L14 L13 M14 M13" for signal <button> in unit <toplevel>.
    Set user-defined property "LOC =  P11 P12 N12 P13 N14 L12 P14 K12" for signal <led> in unit <toplevel>.
    Set user-defined property "LOC =  E13 F14 G14 D14 P16 E14 G13 N15 P15 R16 F13 N16" for signal <ssd> in unit <toplevel>.
    Set user-defined property "LOC =  T3" for signal <io_b1_05> in unit <toplevel>.
    Set user-defined property "LOC =  N11" for signal <io_b1_07> in unit <toplevel>.
    Set user-defined property "LOC =  P10" for signal <io_b1_09> in unit <toplevel>.
Entity <toplevel> analyzed. Unit <toplevel> generated.

Analyzing Entity <dff> (Architecture <behavioral>).
Entity <dff> analyzed. Unit <dff> generated.

Analyzing Entity <debouncer> (Architecture <behavior>).
Entity <debouncer> analyzed. Unit <debouncer> generated.

Analyzing Entity <decoder> (Architecture <behavior>).
Entity <decoder> analyzed. Unit <decoder> generated.

Analyzing Entity <oneshot> (Architecture <behavior>).
Entity <oneshot> analyzed. Unit <oneshot> generated.

Analyzing Entity <counter> (Architecture <behavior>).
Entity <counter> analyzed. Unit <counter> generated.

Analyzing Entity <autorepeat> (Architecture <behaviour>).
Entity <autorepeat> analyzed. Unit <autorepeat> generated.

Analyzing Entity <dpc> (Architecture <behaviour>).
Entity <dpc> analyzed. Unit <dpc> generated.

Analyzing Entity <hex2ssd> (Architecture <behavioral>).
Entity <hex2ssd> analyzed. Unit <hex2ssd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <oneshot>.
    Related source file is "/root/FPGA/Cruise/oneshot.vhd".
    Found 1-bit register for signal <output>.
    Found 32-bit up counter for signal <count>.
    Found 1-bit register for signal <state<0>>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <oneshot> synthesized.


Synthesizing Unit <hex2ssd>.
    Related source file is "/root/FPGA/Cruise/hex2ssd.vhd".
    Found 16x7-bit ROM for signal <$n0033>.
    Found 4x4-bit ROM for signal <$n0034>.
    Found 12-bit register for signal <ssd>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0022> created at line 30.
    Found 11-bit up counter for signal <c>.
    Found 4-bit register for signal <nibble>.
    Summary:
	inferred   2 ROM(s).
	inferred   1 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <hex2ssd> synthesized.


Synthesizing Unit <dpc>.
    Related source file is "/root/FPGA/Cruise/dpc.vhd".
    Found 1-bit register for signal <pulse>.
    Found 32-bit comparator greatequal for signal <$n0002> created at line 28.
    Found 32-bit comparator greatequal for signal <$n0003> created at line 34.
    Found 32-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <dpc> synthesized.


Synthesizing Unit <autorepeat>.
    Related source file is "/root/FPGA/Cruise/autorepeat.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Power Up State     | stdby                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <output>.
    Found 32-bit comparator greater for signal <$n0003> created at line 57.
    Found 32-bit addsub for signal <$n0010> created at line 30.
    Found 32-bit register for signal <counter>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <autorepeat> synthesized.


Synthesizing Unit <counter>.
    Related source file is "/root/FPGA/Cruise/counter.vhd".
    Found finite state machine <FSM_1> for signal <s>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Power Up State     | standby                                        |
    | Encoding           | automatic                                      |