butterfly.vhd

蝶形运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:09:33 02/22/2009 
-- Design Name: 
-- Module Name:    butterfly - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity butterfly is
    Port ( Din1 : in  STD_LOGIC_VECTOR (7 downto 0);
           Din2 : in  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           set : in  STD_LOGIC;
			  reset : in  STD_LOGIC;
           Dout1 : out  STD_LOGIC_VECTOR (12 downto 0);
           Dout2 : out  STD_LOGIC_VECTOR (12 downto 0));
end butterfly;

architecture Behavioral of butterfly is
signal DATA_in1 : STD_LOGIC_VECTOR (12 downto 0):=(others => '0');
signal DATA_in2 : STD_LOGIC_VECTOR (12 downto 0):=(others => '0');
begin

Dout1 <= DATA_in1 + DATA_in2;
Dout2 <= DATA_in2 - DATA_in1;

process(clk,reset,set,Din1,Din2)
begin
  if (reset = '1') then
    
    DATA_in1 <= (others => '0');
	 DATA_in2 <= (others => '0');
	 
  elsif (clk'event and clk = '1') then
	   
		if (set = '1') then
		  DATA_in1 <= "00"&Din1&"000";
        DATA_in2 <= "00"&Din2&"000";
		 end if;
  
		
  end if;
  	  
end process;

end Behavioral;