barrel_shifter.vhd

VHDL实现的桶型移位器

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:59:48 02/22/2009 
-- Design Name: 
-- Module Name:    barrel_shifter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity barrel_shifter is
    Port ( DATA_in : in  STD_LOGIC_VECTOR (12 downto 0);
           clk : in  STD_LOGIC;
           en : in  STD_LOGIC;
			  step_lenth:in  STD_LOGIC_VECTOR (3 downto 0);
           R_L : in  STD_LOGIC;
           DATA_out : out  STD_LOGIC_VECTOR (12 downto 0);
           done : out  STD_LOGIC);
end barrel_shifter;

architecture Behavioral of barrel_shifter is
signal Din_bit,Dout_bit : bit_vector(12 downto 0);
signal S_int : integer range 12 downto 0;
--signal Dsign : bit;
begin
   Din_bit <= to_bitvector(DATA_in);
   S_int <= conv_integer(step_lenth);	
	
	
   process(clk)
	begin
	   if (clk'event and clk = '1') then
		    if (en = '0') then
			    DATA_out <= DATA_in;
			 else
			    if (R_L = '1') then
				    Dout_bit <= Din_bit sra S_int;
					 
				 else
				    Dout_bit(11 downto 0) <= Din_bit(11 downto 0) sll S_int;
				    Dout_bit(12) <= Din_bit(12);
					 
				 end if;
				 DATA_out <= to_stdlogicvector(Dout_bit);
			    done <= '1'; 
			 end if;
		end if;
	end process;

end Behavioral;