clkgen.rpt

基于FPGS的数字秒表设计文件 含有计时

                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (32)    25    B       SOFT      t        0      0   0    0    4    0    1  |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
 (33)    24    B       SOFT      t        0      0   0    0    5    0    1  |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
 (34)    23    B       SOFT      t        0      0   0    0    6    0    1  |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
 (41)    17    B       DFFE   +  t        0      0   0    0    7    1    4  cnter5 (:3)
 (31)    26    B       DFFE   +  t        0      0   0    0    7    1    5  cnter4 (:4)
 (39)    19    B       DFFE   +  t        0      0   0    0    7    1    6  cnter3 (:5)
 (38)    20    B       TFFE   +  t        0      0   0    0    2    1    6  cnter2 (:6)
 (37)    21    B       TFFE   +  t        0      0   0    0    1    1    7  cnter1 (:7)
 (36)    22    B       TFFE   +  t        0      0   0    0    0    1    8  cnter0 (:8)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               f:\keshe\clkgen.rpt
clkgen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC25 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
        | +----------------- LC24 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
        | | +--------------- LC23 |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
        | | | +------------- LC18 newclk
        | | | | +----------- LC17 cnter5
        | | | | | +--------- LC26 cnter4
        | | | | | | +------- LC19 cnter3
        | | | | | | | +----- LC20 cnter2
        | | | | | | | | +--- LC21 cnter1
        | | | | | | | | | +- LC22 cnter0
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC25 -> - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
LC24 -> - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
LC23 -> - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
LC17 -> - - * * * * * - - - | - * | <-- cnter5
LC26 -> - * * * * * * - - - | - * | <-- cnter4
LC19 -> * * * * * * * - - - | - * | <-- cnter3
LC20 -> * * * * * * * * - - | - * | <-- cnter2
LC21 -> * * * * * * * * * - | - * | <-- cnter1
LC22 -> * * * * * * * * * * | - * | <-- cnter0

Pin
43   -> - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               f:\keshe\clkgen.rpt
clkgen

** EQUATIONS **

clk      : INPUT;

-- Node name is ':8' = 'cnter0' 
-- Equation name is 'cnter0', location is LC022, type is buried.
cnter0   = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':7' = 'cnter1' 
-- Equation name is 'cnter1', location is LC021, type is buried.
cnter1   = TFFE( cnter0, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':6' = 'cnter2' 
-- Equation name is 'cnter2', location is LC020, type is buried.
cnter2   = TFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  cnter0 &  cnter1;

-- Node name is ':5' = 'cnter3' 
-- Equation name is 'cnter3', location is LC019, type is buried.
cnter3   = DFFE( _EQ002 $  _LC025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  cnter0 &  cnter1 &  cnter2 & !cnter3 & !cnter4 &  cnter5 & 
              _LC025;

-- Node name is ':4' = 'cnter4' 
-- Equation name is 'cnter4', location is LC026, type is buried.
cnter4   = DFFE( _EQ003 $  _LC024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  cnter0 &  cnter1 &  cnter2 & !cnter3 & !cnter4 &  cnter5 & 
              _LC024;

-- Node name is ':3' = 'cnter5' 
-- Equation name is 'cnter5', location is LC017, type is buried.
cnter5   = DFFE( _EQ004 $  _LC023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  cnter0 &  cnter1 &  cnter2 & !cnter3 & !cnter4 &  cnter5 & 
              _LC023;

-- Node name is 'newclk' 
-- Equation name is 'newclk', location is LC018, type is output.
 newclk  = LCELL( _EQ005 $  GND);
  _EQ005 =  cnter0 &  cnter1 &  cnter2 & !cnter3 & !cnter4 &  cnter5;

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( cnter3 $  _EQ006);
  _EQ006 =  cnter0 &  cnter1 &  cnter2;

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( cnter4 $  _EQ007);
  _EQ007 =  cnter0 &  cnter1 &  cnter2 &  cnter3;

-- Node name is '|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( cnter5 $  _EQ008);
  _EQ008 =  cnter0 &  cnter1 &  cnter2 &  cnter3 &  cnter4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        f:\keshe\clkgen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,125K