translater38.v

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module translater38(data_in,led_out);

input  [2:0] data_in;
output [7:0] led_out;
reg    [7:0] led_out;
always @ (data_in[0] or data_in[1] or data_in[2])
case(data_in)			
3'b000 : led_out = 8'b0000_0001;
3'b001 : led_out = 8'b0000_0010;
3'b010 : led_out = 8'b0000_0100;
3'b011 : led_out = 8'b0000_1000;
3'b100 : led_out = 8'b0001_0000;
3'b101 : led_out = 8'b0010_0000;
3'b110 : led_out = 8'b0100_0000;
3'b111 : led_out = 8'b1000_0000;
endcase
endmodule