translater.v

来自「压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导」· Verilog 代码 · 共 13 行

module yimaqi(data_in,led_out);

input  [1:0] data_in;
output [3:0] led_out;
reg    [3:0] led_out;
always @ (data_in[0] or data_in[1])
case(data_in)			
2'b00 : led_out = 4'b0001;
2'b01 : led_out = 4'b0010;
2'b10 : led_out = 4'b0100;
2'b11 : led_out = 4'b1000;
endcase
endmodule