write_file.v

来自「压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导」· Verilog 代码 · 共 21 行

module test;
  reg [0:2] mm [0:63];
  reg  [0:2] mm1 [0:63];
  integer Vec_File,i;
initial
begin
for(i=0;i<64;i=i+1)
    mm[i]=3'b111;
end
initial
begin
Vec_File=$fopen("E:/div1.dat");
for (i=0;i<64;i=i+1)
    $fdisplayh(Vec_File,"%h ",mm[i]);
$display("file generated");
$fclose(Vec_File);
$readmemh("E:/div1.dat",mm1);
for (i=0;i<64;i=i+1)
   $display("mm1[%d]=  %d",i,mm1[i]);
end
endmodule