ram_control.fit.eqn

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--D1_q_b[0] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[0] at M4K_X17_Y2
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 16, Port A Width: 4, Port B Depth: 16, Port B Width: 4
--Port A Logical Depth: 16, Port A Logical Width: 4, Port B Logical Depth: 16, Port B Logical Width: 4
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
D1_q_b[0]_PORT_A_data_in = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_data_in_reg = DFFE(D1_q_b[0]_PORT_A_data_in, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_address_reg = DFFE(D1_q_b[0]_PORT_A_address, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[0]_PORT_B_address_reg = DFFE(D1_q_b[0]_PORT_B_address, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_PORT_A_write_enable = VCC;
D1_q_b[0]_PORT_A_write_enable_reg = DFFE(D1_q_b[0]_PORT_A_write_enable, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_read_enable = VCC;
D1_q_b[0]_PORT_B_read_enable_reg = DFFE(D1_q_b[0]_PORT_B_read_enable, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_clock_0 = GLOBAL(clk);
D1_q_b[0]_clock_1 = GLOBAL(clk);
D1_q_b[0]_clock_enable_0 = wren;
D1_q_b[0]_PORT_B_data_out = MEMORY(D1_q_b[0]_PORT_A_data_in_reg, , D1_q_b[0]_PORT_A_address_reg, D1_q_b[0]_PORT_B_address_reg, D1_q_b[0]_PORT_A_write_enable_reg, D1_q_b[0]_PORT_B_read_enable_reg, , , D1_q_b[0]_clock_0, D1_q_b[0]_clock_1, D1_q_b[0]_clock_enable_0, , , );
D1_q_b[0] = D1_q_b[0]_PORT_B_data_out[0];

--D1_q_b[3] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[3] at M4K_X17_Y2
D1_q_b[0]_PORT_A_data_in = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_data_in_reg = DFFE(D1_q_b[0]_PORT_A_data_in, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_address_reg = DFFE(D1_q_b[0]_PORT_A_address, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[0]_PORT_B_address_reg = DFFE(D1_q_b[0]_PORT_B_address, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_PORT_A_write_enable = VCC;
D1_q_b[0]_PORT_A_write_enable_reg = DFFE(D1_q_b[0]_PORT_A_write_enable, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_read_enable = VCC;
D1_q_b[0]_PORT_B_read_enable_reg = DFFE(D1_q_b[0]_PORT_B_read_enable, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_clock_0 = GLOBAL(clk);
D1_q_b[0]_clock_1 = GLOBAL(clk);
D1_q_b[0]_clock_enable_0 = wren;
D1_q_b[0]_PORT_B_data_out = MEMORY(D1_q_b[0]_PORT_A_data_in_reg, , D1_q_b[0]_PORT_A_address_reg, D1_q_b[0]_PORT_B_address_reg, D1_q_b[0]_PORT_A_write_enable_reg, D1_q_b[0]_PORT_B_read_enable_reg, , , D1_q_b[0]_clock_0, D1_q_b[0]_clock_1, D1_q_b[0]_clock_enable_0, , , );
D1_q_b[3] = D1_q_b[0]_PORT_B_data_out[3];

--D1_q_b[2] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[2] at M4K_X17_Y2
D1_q_b[0]_PORT_A_data_in = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_data_in_reg = DFFE(D1_q_b[0]_PORT_A_data_in, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_address_reg = DFFE(D1_q_b[0]_PORT_A_address, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[0]_PORT_B_address_reg = DFFE(D1_q_b[0]_PORT_B_address, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_PORT_A_write_enable = VCC;
D1_q_b[0]_PORT_A_write_enable_reg = DFFE(D1_q_b[0]_PORT_A_write_enable, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_read_enable = VCC;
D1_q_b[0]_PORT_B_read_enable_reg = DFFE(D1_q_b[0]_PORT_B_read_enable, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_clock_0 = GLOBAL(clk);
D1_q_b[0]_clock_1 = GLOBAL(clk);
D1_q_b[0]_clock_enable_0 = wren;
D1_q_b[0]_PORT_B_data_out = MEMORY(D1_q_b[0]_PORT_A_data_in_reg, , D1_q_b[0]_PORT_A_address_reg, D1_q_b[0]_PORT_B_address_reg, D1_q_b[0]_PORT_A_write_enable_reg, D1_q_b[0]_PORT_B_read_enable_reg, , , D1_q_b[0]_clock_0, D1_q_b[0]_clock_1, D1_q_b[0]_clock_enable_0, , , );
D1_q_b[2] = D1_q_b[0]_PORT_B_data_out[2];

--D1_q_b[1] is RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|q_b[1] at M4K_X17_Y2
D1_q_b[0]_PORT_A_data_in = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_data_in_reg = DFFE(D1_q_b[0]_PORT_A_data_in, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_A_address = BUS(data[0], data[1], data[2], wraddress[3]);
D1_q_b[0]_PORT_A_address_reg = DFFE(D1_q_b[0]_PORT_A_address, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_address = BUS(rdaddress[0], rdaddress[1], rdaddress[2], rdaddress[3]);
D1_q_b[0]_PORT_B_address_reg = DFFE(D1_q_b[0]_PORT_B_address, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_PORT_A_write_enable = VCC;
D1_q_b[0]_PORT_A_write_enable_reg = DFFE(D1_q_b[0]_PORT_A_write_enable, D1_q_b[0]_clock_0, , , D1_q_b[0]_clock_enable_0);
D1_q_b[0]_PORT_B_read_enable = VCC;
D1_q_b[0]_PORT_B_read_enable_reg = DFFE(D1_q_b[0]_PORT_B_read_enable, D1_q_b[0]_clock_1, , , );
D1_q_b[0]_clock_0 = GLOBAL(clk);
D1_q_b[0]_clock_1 = GLOBAL(clk);
D1_q_b[0]_clock_enable_0 = wren;
D1_q_b[0]_PORT_B_data_out = MEMORY(D1_q_b[0]_PORT_A_data_in_reg, , D1_q_b[0]_PORT_A_address_reg, D1_q_b[0]_PORT_B_address_reg, D1_q_b[0]_PORT_A_write_enable_reg, D1_q_b[0]_PORT_B_read_enable_reg, , , D1_q_b[0]_clock_0, D1_q_b[0]_clock_1, D1_q_b[0]_clock_enable_0, , , );
D1_q_b[1] = D1_q_b[0]_PORT_B_data_out[1];


--wren is wren at LC_X16_Y2_N5
--operation mode is normal

wren_lut_out = state.STATE2 & (wren) # !state.STATE2 & (wren & A1L33 # !A1L23);
wren = DFFEAS(wren_lut_out, GLOBAL(clk), VCC, , , , , !rst, );


--data[0] is data[0] at LC_X15_Y2_N8
--operation mode is normal

data[0]_lut_out = rst & (countwr[0]);
data[0] = DFFEAS(data[0]_lut_out, GLOBAL(clk), VCC, , A1L81, , , , );


--data[1] is data[1] at LC_X15_Y2_N2
--operation mode is normal

data[1]_lut_out = rst & countwr[1];
data[1] = DFFEAS(data[1]_lut_out, GLOBAL(clk), VCC, , A1L81, , , , );


--data[2] is data[2] at LC_X15_Y2_N5
--operation mode is normal

data[2]_lut_out = rst & countwr[2];
data[2] = DFFEAS(data[2]_lut_out, GLOBAL(clk), VCC, , A1L81, , , , );


--wraddress[3] is wraddress[3] at LC_X15_Y2_N4
--operation mode is normal

wraddress[3]_lut_out = rst & (countwr[3]);
wraddress[3] = DFFEAS(wraddress[3]_lut_out, GLOBAL(clk), VCC, , A1L81, , , , );


--rdaddress[0] is rdaddress[0] at LC_X14_Y2_N7
--operation mode is normal

rdaddress[0]_lut_out = !rdaddress[0] & (rst);
rdaddress[0] = DFFEAS(rdaddress[0]_lut_out, GLOBAL(clk), VCC, , A1L82, , , , );


--rdaddress[1] is rdaddress[1] at LC_X14_Y2_N8
--operation mode is normal

rdaddress[1]_lut_out = rdaddress[1] $ rdaddress[0];
rdaddress[1] = DFFEAS(rdaddress[1]_lut_out, GLOBAL(clk), VCC, , A1L82, , , !rst, );


--rdaddress[2] is rdaddress[2] at LC_X16_Y2_N8
--operation mode is normal

rdaddress[2]_lut_out = rdaddress[2] $ (rdaddress[0] & rdaddress[1]);
rdaddress[2] = DFFEAS(rdaddress[2]_lut_out, GLOBAL(clk), VCC, , A1L82, , , !rst, );


--rdaddress[3] is rdaddress[3] at LC_X14_Y2_N5
--operation mode is normal

rdaddress[3]_lut_out = rdaddress[3] $ (rdaddress[0] & rdaddress[2] & rdaddress[1]);
rdaddress[3] = DFFEAS(rdaddress[3]_lut_out, GLOBAL(clk), VCC, , A1L82, , , !rst, );


--countwr[4] is countwr[4] at LC_X14_Y2_N4
--operation mode is normal

countwr[4]_lut_out = countwr[4] $ !A1L31;
countwr[4] = DFFEAS(countwr[4]_lut_out, GLOBAL(clk), VCC, , , , , !rst, );


--countwr[0] is countwr[0] at LC_X14_Y2_N0
--operation mode is arithmetic

countwr[0]_lut_out = state.STATE2 $ !countwr[0];
countwr[0] = DFFEAS(countwr[0]_lut_out, GLOBAL(clk), VCC, , , , , !rst, );

--A1L4 is countwr[0]~131 at LC_X14_Y2_N0
--operation mode is arithmetic

A1L4_cout_0 = !state.STATE2 & countwr[0];
A1L4 = CARRY(A1L4_cout_0);

--A1L5 is countwr[0]~131COUT1_147 at LC_X14_Y2_N0
--operation mode is arithmetic

A1L5_cout_1 = !state.STATE2 & countwr[0];
A1L5 = CARRY(A1L5_cout_1);


--countwr[1] is countwr[1] at LC_X14_Y2_N1
--operation mode is arithmetic

countwr[1]_lut_out = countwr[1] $ (A1L4);
countwr[1] = DFFEAS(countwr[1]_lut_out, GLOBAL(clk), VCC, , , , , !rst, );

--A1L7 is countwr[1]~135 at LC_X14_Y2_N1
--operation mode is arithmetic

A1L7_cout_0 = !A1L4 # !countwr[1];
A1L7 = CARRY(A1L7_cout_0);

--A1L8 is countwr[1]~135COUT1 at LC_X14_Y2_N1
--operation mode is arithmetic

A1L8_cout_1 = !A1L5 # !countwr[1];
A1L8 = CARRY(A1L8_cout_1);


--countwr[2] is countwr[2] at LC_X14_Y2_N2
--operation mode is arithmetic

countwr[2]_lut_out = countwr[2] $ (!A1L7);
countwr[2] = DFFEAS(countwr[2]_lut_out, GLOBAL(clk), VCC, , , , , !rst, );

--A1L01 is countwr[2]~139 at LC_X14_Y2_N2
--operation mode is arithmetic

A1L01_cout_0 = countwr[2] & (!A1L7);
A1L01 = CARRY(A1L01_cout_0);

--A1L11 is countwr[2]~139COUT1_148 at LC_X14_Y2_N2
--operation mode is arithmetic

A1L11_cout_1 = countwr[2] & (!A1L8);
A1L11 = CARRY(A1L11_cout_1);


--countwr[3] is countwr[3] at LC_X14_Y2_N3
--operation mode is arithmetic

countwr[3]_lut_out = countwr[3] $ A1L01;
countwr[3] = DFFEAS(countwr[3]_lut_out, GLOBAL(clk), VCC, , , , , !rst, );

--A1L31 is countwr[3]~143 at LC_X14_Y2_N3
--operation mode is arithmetic

A1L31_cout_0 = !A1L01 # !countwr[3];
A1L31 = CARRY(A1L31_cout_0);

--A1L41 is countwr[3]~143COUT1_149 at LC_X14_Y2_N3
--operation mode is arithmetic

A1L41_cout_1 = !A1L11 # !countwr[3];
A1L41 = CARRY(A1L41_cout_1);


--A1L43 is reduce_nor~22 at LC_X14_Y2_N6
--operation mode is normal

A1L43 = !countwr[1] & !countwr[0] & !countwr[2] & !countwr[3];


--A1L33 is reduce_nor~1 at LC_X16_Y2_N4
--operation mode is normal

A1L33 = !countwr[4] # !A1L43;


--A1L23 is reduce_nor~0 at LC_X16_Y2_N6
--operation mode is normal

A1L23 = countwr[4] # !A1L43;


--state.STATE2 is state.STATE2 at LC_X15_Y2_N6
--operation mode is normal

state.STATE2_lut_out = rst & (countwr[4] # !A1L43);
state.STATE2 = DFFEAS(state.STATE2_lut_out, GLOBAL(clk), VCC, , A1L73, , , , );


--A1L81 is data[0]~61 at LC_X16_Y2_N2
--operation mode is normal

A1L81 = !state.STATE2 # !rst;


--A1L82 is rdaddress[0]~90 at LC_X14_Y2_N9
--operation mode is normal

A1L82 = state.STATE2 # countwr[4] & A1L43 # !rst;


--A1L73 is state~122 at LC_X16_Y2_N9
--operation mode is normal

A1L73 = !state.STATE2 & A1L43 # !rst;


--clk is clk at PIN_29
--operation mode is input

clk = INPUT();


--rst is rst at PIN_85
--operation mode is input

rst = INPUT();


--q[0] is q[0] at PIN_87
--operation mode is output

q[0] = OUTPUT(D1_q_b[0]);


--q[1] is q[1] at PIN_88
--operation mode is output

q[1] = OUTPUT(D1_q_b[1]);


--q[2] is q[2] at PIN_95
--operation mode is output

q[2] = OUTPUT(D1_q_b[2]);


--q[3] is q[3] at PIN_94
--operation mode is output

q[3] = OUTPUT(D1_q_b[3]);