ram_control.fit.qmsg

压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 29 13:33:19 2006 " "Info: Processing started: Sat Jul 29 13:33:19 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ram_control -c ram_control " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ram_control -c ram_control" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ram_control EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"ram_control\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "6 6 " "Info: No exact pin location assignment(s) for 6 pins of 6 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[0\] " "Info: Pin q\[0\] not assigned to an exact location on the device" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[0\]" } } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { q[0] } "NODE_NAME" } "" } } { "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" "" { q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[1\] " "Info: Pin q\[1\] not assigned to an exact location on the device" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[1\]" } } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { q[1] } "NODE_NAME" } "" } } { "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" "" { q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[2\] " "Info: Pin q\[2\] not assigned to an exact location on the device" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[2\]" } } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { q[2] } "NODE_NAME" } "" } } { "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" "" { q[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[3\] " "Info: Pin q\[3\] not assigned to an exact location on the device" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[3\]" } } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { q[3] } "NODE_NAME" } "" } } { "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" "" { q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { clk } "NODE_NAME" } "" } } { "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" "" { Report "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control_cmp.qrpt" Compiler "ram_control" "UNKNOWN" "V1" "E:/farsight_fpga_course/code/high/onchip ram/test/db/ram_control.quartus_db" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/" "" "" { rst } "NODE_NAME" } "" } } { "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" { Floorplan "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.fld" "" "" { rst } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "ram_control.v" "" { Text "E:/farsight_fpga_course/code/high/onchip ram/test/ram_control.v" 2 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}