_primary.vhd

来自「压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity cyclone_jtag is
    generic(
        lpm_type        : string  := "cyclone_jtag"
    );
    port(
        tms             : in     vl_logic;
        tck             : in     vl_logic;
        tdi             : in     vl_logic;
        ntrst           : in     vl_logic;
        tdoutap         : in     vl_logic;
        tdouser         : in     vl_logic;
        tdo             : out    vl_logic;
        tmsutap         : out    vl_logic;
        tckutap         : out    vl_logic;
        tdiutap         : out    vl_logic;
        shiftuser       : out    vl_logic;
        clkdruser       : out    vl_logic;
        updateuser      : out    vl_logic;
        runidleuser     : out    vl_logic;
        usr1user        : out    vl_logic
    );
end cyclone_jtag;