_primary.vhd

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library verilog;
use verilog.vl_types.all;
entity sram_test is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        data1           : inout  vl_logic_vector(7 downto 0);
        addr1           : out    vl_logic_vector(17 downto 0);
        ce1             : out    vl_logic;
        we1             : out    vl_logic;
        oe1             : out    vl_logic;
        data2           : inout  vl_logic_vector(7 downto 0);
        addr2           : out    vl_logic_vector(17 downto 0);
        ce2             : out    vl_logic;
        we2             : out    vl_logic;
        oe2             : out    vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        data_in_en      : in     vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0)
    );
end sram_test;