_primary.vhd

来自「压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity sram is
    port(
        addr            : in     vl_logic_vector(20 downto 0);
        data            : inout  vl_logic_vector(7 downto 0);
        wr              : in     vl_logic;
        rd              : in     vl_logic;
        ce              : in     vl_logic
    );
end sram;