ram_control.v

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module ram_control(q,clk,rst);
input clk,rst;
output [3:0] q;

wire [3:0] q;
reg [3:0] data;    
reg wren;           
reg [3:0] wraddress;
reg [3:0] rdaddress;
reg [4:0] countwr;
reg [1:0] state;
parameter STATE1=2'b01;
parameter STATE2=2'b10;

assign wrclock=clk;
assign rdclock=clk;

always @ (posedge clk)
	if(!rst)
		begin
			data<='d0;
			wren<=1'b0;
			wraddress<=4'd0;
			rdaddress<=4'd0;
			countwr<=5'd0;
			state<=STATE1;
		end
	else
		begin
			case(state)
			STATE1:
				begin
					data<=countwr[3:0];
					wraddress<=countwr;
					countwr<=countwr+1'b1;
					if(countwr==5'd0)
						begin
							wren<=1;
							state<=STATE1;
						end
					else if(countwr==5'd16)
						begin
							wren<=0;
							rdaddress<=rdaddress+1;
							state<=STATE2;
						end
				end
			STATE2:
				begin
					rdaddress<=rdaddress+1;
				end
			endcase
		end
RAM_36 RAM_36(.data(data),.wren(wren),.wraddress(wraddress),
			.rdaddress(rdaddress),.wrclock(wrclock),.rdclock(rdclock),.q(q));
endmodule