📄 ram_control.map.rpt
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; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 64 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |ram_control|RAM_36:RAM_36|altsyncram:altsyncram_component ;
; |altsyncram_e181:auto_generated| ; 0 (0) ; 0 ; 64 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |ram_control|RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 4 ; 16 ; 4 ; 64 ; None ;
+-----------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+------------------------------------+
; State Machine - |ram_control|state ;
+--------------+---------------------+
; Name ; state.STATE2 ;
+--------------+---------------------+
; state.STATE1 ; 0 ;
; state.STATE2 ; 1 ;
+--------------+---------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 15 ;
; Number of registers using Synchronous Clear ; 9 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 9 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |ram_control|data[0] ;
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |ram_control|rdaddress[0] ;
; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; No ; |ram_control|state~7 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |ram_control ;
+----------------+-------+----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+----------------------------------------------------+
; STATE1 ; 01 ; Binary ;
; STATE2 ; 10 ; Binary ;
+----------------+-------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: RAM_36:RAM_36|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------+-------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 4 ; Integer ;
; WIDTHAD_A ; 4 ; Integer ;
; NUMWORDS_A ; 16 ; Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 4 ; Integer ;
; WIDTHAD_B ; 4 ; Integer ;
; NUMWORDS_B ; 16 ; Integer ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_e181 ; Untyped ;
+------------------------------------+-----------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Sat Jul 29 11:10:09 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram_control -c ram_control
Info: Found 1 design units, including 1 entities, in source file RAM_36.v
Info: Found entity 1: RAM_36
Warning: Verilog HDL net warning at ram_control.v(15): created undeclared net "wrclock"
Warning: Verilog HDL net warning at ram_control.v(16): created undeclared net "rdclock"
Info: Found 1 design units, including 1 entities, in source file ram_control.v
Info: Found entity 1: ram_control
Info: Elaborating entity "ram_control" for the top level hierarchy
Warning: Verilog HDL assignment warning at ram_control.v(21): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at ram_control.v(34): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at ram_control.v(38): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ram_control.v(43): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ram_control.v(44): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at ram_control.v(50): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "RAM_36" for hierarchy "RAM_36:RAM_36"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "RAM_36:RAM_36|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e181.tdf
Info: Found entity 1: altsyncram_e181
Info: Elaborating entity "altsyncram_e181" for hierarchy "RAM_36:RAM_36|altsyncram:altsyncram_component|altsyncram_e181:auto_generated"
Info: Duplicate registers merged to single register
Info: Duplicate register "wraddress[2]" merged to single register "data[2]"
Info: Duplicate register "wraddress[1]" merged to single register "data[1]"
Info: Duplicate register "wraddress[0]" merged to single register "data[0]"
Info: Duplicate register "data[3]" merged to single register "wraddress[3]"
Info: State machine "|ram_control|state" contains 2 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|ram_control|state"
Info: Encoding result for state machine "|ram_control|state"
Info: Completed encoding using 1 state bits
Info: Encoded state bit "state.STATE2"
Info: State "|ram_control|state.STATE1" uses code string "0"
Info: State "|ram_control|state.STATE2" uses code string "1"
Info: Implemented 31 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 4 output pins
Info: Implemented 21 logic cells
Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Processing ended: Sat Jul 29 11:10:12 2006
Info: Elapsed time: 00:00:03
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