ram_control_v.sdo

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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.


// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "ram_control")
  (DATE "07/29/2006 11:10:31")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE clk\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE rst\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1475:1475:1475) (1475:1475:1475))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE countwr\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1109:1109:1109) (1164:1164:1164))
        (PORT datab (521:521:521) (525:525:525))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE countwr\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE countwr\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (528:528:528) (538:538:538))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE countwr\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE countwr\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (552:552:552) (554:554:554))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE countwr\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE countwr\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (527:527:527) (530:530:530))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE countwr\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE countwr\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (517:517:517) (523:523:523))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE countwr\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6472:6472:6472) (6637:6637:6637))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE state\~122_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (867:867:867) (853:853:853))
        (PORT datac (5400:5400:5400) (5522:5522:5522))
        (PORT datad (1268:1268:1268) (1291:1291:1291))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE state\.STATE2\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1154:1154:1154) (1199:1199:1199))
        (PORT datac (5478:5478:5478) (5588:5588:5588))
        (PORT datad (761:761:761) (761:761:761))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE state\.STATE2\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1575:1575:1575) (1621:1621:1621))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE reduce_nor\~22_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (535:535:535) (544:544:544))
        (PORT datab (528:528:528) (533:533:533))
        (PORT datac (556:556:556) (575:575:575))
        (PORT datad (548:548:548) (548:548:548))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE reduce_nor\~0_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1275:1275:1275) (1300:1300:1300))
        (PORT datad (1245:1245:1245) (1266:1266:1266))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE reduce_nor\~1_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1274:1274:1274) (1301:1301:1301))
        (PORT datad (1242:1242:1242) (1264:1264:1264))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE wren\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (406:406:406) (423:423:423))
        (PORT datab (481:481:481) (496:496:496))
        (PORT datac (414:414:414) (445:445:445))
        (PORT datad (862:862:862) (839:839:839))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE wren\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (6504:6504:6504) (6665:6665:6665))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE data\[0\]\~61_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (5402:5402:5402) (5521:5521:5521))
        (PORT datad (866:866:866) (844:844:844))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE data\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (5476:5476:5476) (5568:5568:5568))
        (PORT datac (725:725:725) (758:758:758))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datac regin (478:478:478) (478:478:478))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE data\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1656:1656:1656) (1694:1694:1694))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE data\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (5466:5466:5466) (5578:5578:5578))
        (PORT datad (730:730:730) (738:738:738))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE data\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1434:1434:1434) (1414:1414:1414))
        (PORT ena (1656:1656:1656) (1694:1694:1694))