_primary.vhd

来自「压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity CYCLONE_PRIM_DFFE is
    // This module cannot be connected to from
    // VHDL because it has unnamed ports.
end CYCLONE_PRIM_DFFE;