_primary.vhd

来自「压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity RAM_36 is
    port(
        data            : in     vl_logic_vector(3 downto 0);
        wren            : in     vl_logic;
        wraddress       : in     vl_logic_vector(3 downto 0);
        rdaddress       : in     vl_logic_vector(3 downto 0);
        wrclock         : in     vl_logic;
        rdclock         : in     vl_logic;
        q               : out    vl_logic_vector(3 downto 0)
    );
end RAM_36;